NXP Semiconductors LPC11U3x

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 451 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
If lockup state occurs in the NMI handler a subsequent NMI does not cause the processor
to leave lockup state.
24.3.5 Power management
The Cortex-M0 processor sleep modes reduce power consumption:
• a sleep mode, that stops the processor clock
• a Deep-sleep and Power-down modes, for details see Section 3.9.
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see
Section 24–24.5.3.5
.
This section describes the mechanisms for entering sleep mode, and the conditions for
waking up from sleep mode.
24.3.5.1 Entering sleep mode
This section describes the mechanisms software can use to put the processor into sleep
mode.
The system can generate spurious wake-up events, for example a debug operation wakes
up the processor. Therefore software must be able to put the processor back into sleep
mode after such an event. A program might have an idle loop to put the processor back in
to sleep mode.
24.3.5.1.1 Wait for interrupt
The Wait For Interrupt instruction,
WFI , causes immediate entry to sleep mode. When the
processor executes a
WFI instruction it stops executing instructions and enters sleep
mode. See Section 24–24.4.7.12
for more information.
24.3.5.1.2 Wait for event
Remark: The WFE instruction is not implemented on the LPC11U3x/2x/1x.
The Wait For Event instruction,
WFE , causes entry to sleep mode conditional on the value
of a one-bit event register. When the processor executes a
WFE instruction, it checks the
value of the event register:
0 — The processor stops executing instructions and enters sleep mode
1 — The processor sets the register to zero and continues executing instructions without
entering sleep mode.
See Section 24–24.4.7.11
for more information.
If the event register is 1, this indicates that the processor must not enter sleep mode on
execution of a
WFE instruction. Typically, this is because of the assertion of an external
event, or because another processor in the system has executed a
SEV instruction, see
Section 24–24.4.7.9
. Software cannot access this register directly.