UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 482 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
spec_reg is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
24.4.7.7.2 Operation
MSR updates one of the special registers with the value from the register specified by Rn.
See Section 24–24.4.7.6
.
24.4.7.7.3 Restrictions
In this instruction, Rn must not be SP and must not be PC.
24.4.7.7.4 Condition flags
This instruction updates the flags explicitly based on the value in Rn.
24.4.7.7.5 Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
24.4.7.8 NOP
No Operation.
24.4.7.8.1 Syntax
NOP
24.4.7.8.2 Operation
NOP performs no operation and is not guaranteed to be time consuming. The processor
might remove it from the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the subsequent instructions on a 64-bit
boundary.
24.4.7.8.3 Restrictions
There are no restrictions.
24.4.7.8.4 Condition flags
This instruction does not change the flags.
24.4.7.8.5 Examples
NOP ; No operation
24.4.7.9 SEV
Send Event.
24.4.7.9.1 Syntax
SEV
24.4.7.9.2 Operation
SEV causes an event to be signaled to all processors within a multiprocessor system. It
also sets the local event register, see Section 24–24.3.5
.
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