UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 481 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.7.5.3 Restrictions
There are no restrictions.
24.4.7.5.4 Condition flags
This instruction does not change the flags.
24.4.7.5.5 Examples
ISB ; Instruction Synchronisation Barrier
24.4.7.6 MRS
Move the contents of a special register to a general-purpose register.
24.4.7.6.1 Syntax
MRS Rd, spec_reg
where:
Rd is the general-purpose destination register.
spec_reg is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR, IAPSR,
EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
24.4.7.6.2 Operation
MRS stores the contents of a special-purpose register to a general-purpose register. The
MRS instruction can be combined with the MR instruction to produce read-modify-write
sequences, which are suitable for modifying a specific flag in the PSR.
See Section 24–24.4.7.7
.
24.4.7.6.3 Restrictions
In this instruction, Rd must not be SP or PC.
24.4.7.6.4 Condition flags
This instruction does not change the flags.
24.4.7.6.5 Examples
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
24.4.7.7 MSR
Move the contents of a general-purpose register into the specified special register.
24.4.7.7.1 Syntax
MSR spec_reg, Rn
where:
Rn is the general-purpose source register.
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