UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 480 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.7.3.2 Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that
appear in program order before the DMB instruction are observed before any explicit
memory accesses that appear in program order after the DMB instruction. DMB does not
affect the ordering of instructions that do not access memory.
24.4.7.3.3 Restrictions
There are no restrictions.
24.4.7.3.4 Condition flags
This instruction does not change the flags.
24.4.7.3.5 Examples
DMB ; Data Memory Barrier
24.4.7.4 DSB
Data Synchronization Barrier.
24.4.7.4.1 Syntax
DSB
24.4.7.4.2 Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after
the DSB, in program order, do not execute until the DSB instruction completes. The DSB
instruction completes when all explicit memory accesses before it complete.
24.4.7.4.3 Restrictions
There are no restrictions.
24.4.7.4.4 Condition flags
This instruction does not change the flags.
24.4.7.4.5 Examples
DSB ; Data Synchronisation Barrier
24.4.7.5 ISB
Instruction Synchronization Barrier.
24.4.7.5.1 Syntax
ISB
24.4.7.5.2 Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
so that all instructions following the ISB are fetched from cache or memory again, after the
ISB instruction has been completed.
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