UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 464 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.4.3.3 Restrictions
In these instructions:
• Rt, Rn, and Rm must only specify R0-R7.
• the computed memory address must be divisible by the number of bytes in the load or
store, see Section 24–24.4.3.4
.
24.4.4.3.4 Condition flags
These instructions do not change the flags.
24.4.4.3.5 Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
; sum of R5 and R1
LDRSH R1, [R2, R3] ; Load a halfword from the memory address
; specified by (R2 + R3), sign extend to 32-bits
; and write to R1.
24.4.4.4 LDR, PC-relative
Load register (literal) from memory.
24.4.4.4.1 Syntax
LDR Rt, label
where:
Rt is the register to load.
label is a PC-relative expression. See Section 24–24.4.3.5
.
24.4.4.4.2 Operation
Loads the register specified by Rt from the word in memory specified by label.
24.4.4.4.3 Restrictions
In these instructions, label must be within 1020 bytes of the current PC and word aligned.
24.4.4.4.4 Condition flags
These instructions do not change the flags.
24.4.4.4.5 Examples
LDR R0, LookUpTable ; Load R0 with a word of data from an address
; labelled as LookUpTable.
LDR R3, [PC, #100] ; Load R3 with memory word at (PC + 100).
24.4.4.5 LDM and STM
Load and Store Multiple registers.
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