UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 459 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
• If n is 32, then the value of the result is same as the value in Rm, and if the carry flag
is updated, it is updated to bit[31] of Rm.
• ROR
with shift length, n, greater than 32 is the same as
ROR
with shift length n-32.
24.4.3.4 Address alignment
An aligned access is an operation where a word-aligned address is used for a word, or
multiple word access, or where a halfword-aligned address is used for a halfword access.
Byte accesses are always aligned.
There is no support for unaligned accesses on the Cortex-M0 processor. Any attempt to
perform an unaligned memory access operation results in a HardFault exception.
24.4.3.5 PC-relative expressions
A PC-relative expression or label is a symbol that represents the address of an instruction
or literal data. It is represented in the instruction as the PC value plus or minus a numeric
offset. The assembler calculates the required offset from the label and the address of the
current instruction. If the offset is too big, the assembler produces an error.
Remark:
• For most instructions, the value of the PC is the address of the current instruction plus
4 bytes.
• Your assembler might permit other syntaxes for PC-relative expressions, such as a
label plus or minus a number, or an expression of the form [PC, #imm].
24.4.3.6 Conditional execution
Most data processing instructions update the condition flags in the Application Program
Status Register (APSR) according to the result of the operation, see Section
. Some
instructions update all flags, and some only update a subset. If a flag is not updated, the
original value is preserved. See the instruction descriptions for the flags they affect.
You can execute a conditional branch instruction, based on the condition flags set in
another instruction, either:
• immediately after the instruction that updated the flags
• after any number of intervening instructions that have not updated the flags.
Fig 85. ROR #3
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