UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 495 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.5.3.7 System Handler Priority Registers
The SHPR2-SHPR3 registers set the priority level, 0 to 3, of the exception handlers that
have configurable priority.
SHPR2-SHPR3 are word accessible. See the register summary in Table 24–442
for their
attributes.
To access to the system exception priority level using CMSIS, use the following CMSIS
functions:
•
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
•
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
The input parameter
IRQn
is the IRQ number, see Table 24–421 for more information.
The system fault handlers, and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
24.5.3.7.1 System Handler Priority Register 2
The bit assignments are:
24.5.3.7.2 System Handler Priority Register 3
The bit assignments are:
Table 447. CCR bit assignments
Bits Name Function
[31:10] - Reserved.
[9] STKALIGN Always reads as one, indicates 8-byte stack alignment on
exception entry.
On exception entry, the processor uses bit[9] of the stacked PSR
to indicate the stack alignment. On return from the exception it
uses this stacked bit to restore the correct stack alignment.
[8:4] - Reserved.
[3] UNALIGN_TRP Always reads as one, indicates that all unaligned accesses
generate a HardFault.
[2:0] - Reserved.
Table 448. System fault handler priority fields
Handler Field Register description
SVCall PRI_11 Section 24–24.5.3.7.1
PendSV PRI_14 Section 24–24.5.3.7.2
SysTick PRI_15
Table 449. SHPR2 register bit assignments
Bits Name Function
[31:24] PRI_11 Priority of system handler 11, SVCall
[23:0] - Reserved
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