NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 505 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
0x4003 C010) bit description . . . . . . . . . . . . . .45
Table 50. Peripheral configuration in reduced power modes
47
Table 51. PLL frequency parameters . . . . . . . . . . . . . . . .55
Table 52. PLL configuration examples . . . . . . . . . . . . . . .55
Table 53. Register overview: PMU (base address 0x4003
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 54. Power control register (PCON, address 0x4003
8000) bit description . . . . . . . . . . . . . . . . . . . .56
Table 55. General purpose registers 0 to 3 (GPREG[0:3],
address 0x4003 8004 (GPREG0) to 0x4003 8010
(GPREG3)) bit description . . . . . . . . . . . . . . .57
Table 56. General purpose register 4 (GPREG4, address
0x4003 8014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 57. set_pll routine . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 58. set_power routine . . . . . . . . . . . . . . . . . . . . . .65
Table 59. Connection of interrupt sources to the Vectored
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . .68
Table 60. Register overview: NVIC (base address 0xE000
E000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 61. Interrupt Set Enable Register 0 register (ISER0,
address 0xE000 E100) bit description . . . . . .71
Table 62. Interrupt clear enable register 0 (ICER0, address
0xE000 E180) . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 63. Interrupt set pending register 0 register (ISPR0,
address 0xE000 E200) bit description . . . . . . .73
Table 64. Interrupt clear pending register 0 register (ICPR0,
address 0xE000 E280) bit description . . . . . . .74
Table 65. Interrupt Active Bit Register 0 (IABR0, address
0xE000 E300) bit description . . . . . . . . . . . . .75
Table 66. Interrupt Priority Register 0 (IPR0, address
0xE000 E400) bit description . . . . . . . . . . . . . .76
Table 67. Interrupt Priority Register 1 (IPR1, address
0xE000 E404) bit description . . . . . . . . . . . . .77
Table 68. Interrupt Priority Register 2 (IPR2, address
0xE000 E408) bit description . . . . . . . . . . . . . .77
Table 69. Interrupt Priority Register 3 (IPR3, address
0xE000 E40C) bit description. . . . . . . . . . . . . .77
Table 70. Interrupt Priority Register 4 (IPR4, address
0xE000 E410) bit description . . . . . . . . . . . . . .78
Table 71. Interrupt Priority Register 5 (IPR5, address
0xE000 E414) bit description . . . . . . . . . . . . . .78
Table 72. Interrupt Priority Register 6 (IPR6, address
0xE000 E418) bit description . . . . . . . . . . . . . .78
Table 73. Interrupt Priority Register 7 (IPR7, address
0xE000 E41C) bit description. . . . . . . . . . . . . .79
Table 74. IOCON registers available . . . . . . . . . . . . . . . .80
Table 75. Register overview: I/O configuration (base
address 0x4004 4000) . . . . . . . . . . . . . . . . . . .84
Table 76. RESET_PIO0_0 register (RESET_PIO0_0,
address 0x4004 4000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 77. PIO0_1 register (PIO0_1, address 0x4004 4004)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 78. PIO0_2 register (PIO0_2, address 0x4004 4008)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 79. PIO0_3 register (PIO0_3, address 0x4004 400C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 80. PIO0_4 register (PIO0_4, address 0x4004 4010)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 81. PIO0_5 register (PIO0_5, address 0x4004 4014)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 82. PIO0_6 register (PIO0_6, address 0x4004 4018)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 83. PIO0_7 register (PIO0_7, address 0x4004 401C)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 84. PIO0_8 register (PIO0_8, address 0x4004 4020)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 85. PIO0_9 register (PIO0_9, address 0x4004 4024)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 86. SWCLK_PIO0_10 register (SWCLK_PIO0_10,
address 0x4004 4028) bit description . . . . . . . 93
Table 87. TDI_PIO0_11 register (TDI_PIO0_11, address
0x4004 402C) bit description . . . . . . . . . . . . . 94
Table 88. TMS_PIO0_12 register (TMS_PIO0_12, address
0x4004 4030) bit description . . . . . . . . . . . . . . 95
Table 89. TDO_PIO0_13 register (TDO_PIO0_13, address
0x4004 4034) bit description . . . . . . . . . . . . . . 96
Table 90. TRST_PIO0_14 register (TRST_PIO0_14,
address 0x4004 4038) bit description . . . . . . 97
Table 91. SWDIO_PIO0_15 register (SWDIO_PIO0_15,
a
ddress 0x40
04 403C) bit description . . . . . . 98
Table 92. PIO0_16 register (PIO0_16, address 0x4004
4040) bit description . . . . . . . . . . . . . . . . . . . . 99
Table 93. PIO0_17 register (PIO0_17, address 0x4004
4044) bit description . . . . . . . . . . . . . . . . . . . 100
Table 94. PIO0_18 register (PIO0_18, address 0x4004
4048) bit description . . . . . . . . . . . . . . . . . . . 100
Table 95. PIO0_19 register (PIO0_19, address 0x4004
404C) bit description . . . . . . . . . . . . . . . . . . . 101
Table 96. PIO0_20 register (PIO0_20, address 0x4004
4050) bit description . . . . . . . . . . . . . . . . . . . 102
Table 97. PIO0_21 register (PIO0_21, address 0x4004
4054) bit description . . . . . . . . . . . . . . . . . . . 103
Table 98. PIO0_22 register (PIO0_22, address 0x4004
4058) bit description . . . . . . . . . . . . . . . . . . . 103
Table 99. PIO0_23 register (PIO0_23, address 0x4004
405C) bit description . . . . . . . . . . . . . . . . . . 104
Table 100. PIO1_0 register (PIO1_0, address 0x4004 4060)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 101. PIO1_1 register (PIO1_1, address 0x4004 4064)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 102. PIO1_2 register (PIO1_2, address 0x4004 4068)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 103. PIO1_3 (PIO1_3, address 0x4004406C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 104. I/O configuration PIO1_4 (PIO1_4, address
0x4004 4070) bit description . . . . . . . . . . . . . 108
Table 105. PIO1_5 register (PIO1_5, address 0x4004 4074)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 106. PIO1_6 register (PIO1_6, address 0x4004 4078)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 107. PIO1_7 register (PIO1_7, address 0x4004 407C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 108. PIO1_8 register (PIO1_8, address 0x4004 4080)

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English