UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 506 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 109. PIO1_9 register (PIO1_9, address 0x4004 4084)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 110. PIO1_10 register (PIO1_10, address 0x4004
4088) bit description . . . . . . . . . . . . . . . . . . .112
Table 111. PIO1_11 register (PIO1_11, address 0x4004
408C) bit description. . . . . . . . . . . . . . . . . . . .113
Table 112. PIO1_12 register (PIO1_12, address 0x4004
4090) bit description . . . . . . . . . . . . . . . . . . . .114
Table 113. PIO1_13 register (PIO1_13, address 0x4004
4094) bit description . . . . . . . . . . . . . . . . . . .114
Table 114. PIO1_14 register (PIO1_14, address 0x4004
4098) bit description . . . . . . . . . . . . . . . . . . .115
Table 115. PIO1_15 register (PIO1_15, address 0x4004
409C) bit description . . . . . . . . . . . . . . . . . . .116
Table 116. PIO1_16 register (PIO1_16, address 0x4004
40A0) bit description . . . . . . . . . . . . . . . . . . .117
Table 117. PIO1_17 register (PIO1_17, address 0x4004
40A4) bit description . . . . . . . . . . . . . . . . . . .117
Table 118. PIO1_18 register (PIO1_18, address 0x4004
40A8) bit description . . . . . . . . . . . . . . . . . . .118
Table 119. PIO1_19 register (PIO1_19, address 0x4004
40AC) bit description . . . . . . . . . . . . . . . . . . .119
Table 120. PIO1_20 register (PIO1_20, address 0x4004
40B0) bit description . . . . . . . . . . . . . . . . . . .120
Table 121. PIO1_21 register (PIO1_21, address 0x4004
40B4) bit description . . . . . . . . . . . . . . . . . . .120
Table 122. PIO1_22 register (PIO1_22, address 0x4004
40B8) bit description . . . . . . . . . . . . . . . . . . .121
Table 123. PIO1_23 register (PIO1_23, address 0x4004
40BC) bit description . . . . . . . . . . . . . . . . . . .122
Table 124. PIO1_24 register (PIO1_24, address 0x4004
40C0) bit description . . . . . . . . . . . . . . . . . . .123
Table 125. PIO1_25 register (PIO1_25, address 0x4004
40C4) bit description . . . . . . . . . . . . . . . . . . .123
Table 126. PIO1_26 register (PIO1_26, address 0x4004
40C8) bit description . . . . . . . . . . . . . . . . . . .124
Table 127. PIO1_27 register (PIO1_27, address 0x4004
40CC) bit description . . . . . . . . . . . . . . . . . . .125
Table 128. PIO1_28 register (PIO1_28, address 0x4004
40D0) bit description . . . . . . . . . . . . . . . . . . .125
Table 129. PIO1_29 register (PIO1_29, address 0x4004
40D4) bit description . . . . . . . . . . . . . . . . . . .126
Table 130. PIO1_31 register (PIO1_31, address 0x4004
40DC) bit description . . . . . . . . . . . . . . . . . . .127
Table 131. LPC11U3x/2x/1x pin configurations. . . . . . . .128
Table 132. LPC11U1x pin description . . . . . . . . . . . . . . .132
Table 133. Multiplexing of peripheral functions . . . . . . . .138
Table 134. LPC11U2x pin description . . . . . . . . . . . . . . .140
Table 135. LPC11U3x pin description . . . . . . . . . . . . . . .145
Table 136. GPIO pins available . . . . . . . . . . . . . . . . . . . .153
Table 137. Register overview: GPIO pin interrupts (base
address: 0x4004 C000) . . . . . . . . . . . . . . . . .155
Table 138. Register overview: GPIO GROUP0 interrupt
(base address 0x4005 C000) . . . . . . . . . . . .155
Table 139. Register overview: GPIO GROUP1 interrupt
(base address 0x4006 0000) . . . . . . . . . . . . .156
Table 140. Register overview: GPIO port (base address
0x5000 0000). . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 141. Pin interrupt mode register (ISEL, address
0x4004 C000) bit description . . . . . . . . . . . . 157
Table 142. Pin interrupt level (rising edge) interrupt enable
register (IENR, address 0x4004 C004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 143. Pin interrupt level (rising edge) interrupt set
register (SIENR, address 0x4004 C008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 144. Pin interrupt level (rising edge interrupt) clear
register (CIENR, address 0x4004 C00C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 145. Pin interrupt active level (falling edge) interrupt
enable register (IENF, address 0x4004 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 146. Pin interrupt active level (falling edge interrupt)
set register (SIENF, address 0x4004 C014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 147. Pin interrupt active level (falling edge) interrupt
clear register (CIENF, address 0x4004 C018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 148. Pin interrupt rising edge register (RISE, address
0x4004 C01C) bit description . . . . . . . . . . . . 160
Table 149. Pin interrupt falling edge register (FALL, address
0x4004 C020) bit description . . . . . . . . . . . . 160
Table 150. Pin interrupt status register (IST address 0x4004
C024) bit description . . . . . . . . . . . . . . . . . . . 161
Table 151. GPIO grouped interrupt control register (CTRL,
addresses 0x4005 C000 (GROUP0 INT) and
0x4006 0000 (GROUP1 INT)) bit description 161
Table 152. GPIO grouped interrupt
port 0
polarity registers
(PORT_POL0, addresses 0x4005 C020
(GROUP0 INT) and 0x4006 0020 (GROUP1 INT))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 153. GPIO grouped interrupt port 1 polarity registers
(PORT_POL1, addresses 0x4005 C024
(GROUP0 INT) and 0x4006 0024 (GROUP1 INT))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 154. GPIO grouped interrupt port 0 enable registers
(PORT_ENA0, addresses 0x4005 C040
(GROUP0 INT) and 0x4006 0040 (GROUP1 INT))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 155. GPIO grouped interrupt port 1 enable registers
(PORT_ENA1, addresses 0x4005 C044
(GROUP0 INT) and 0x4006 0044 (GROUP1 INT))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 156. GPIO port 0 byte pin registers (B0 to B23,
addresses 0x5000 0000 to 0x5000 0018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 157. GPIO port 1 byte pin registers (B32 to B63,
addresses 0x5000 0020 to 0x5000 002F) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 158. GPIO port 0 word pin registers (W0 to W23,
addresses 0x5000 1000 to 0x5000 1060) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 159. GPIO port 1 word pin registers (W32 to W63,
addresses 0x5000 1080 to 0x5000 10FC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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