NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 504 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
25.4 Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .8
Table 2. Part ordering options . . . . . . . . . . . . . . . . . . . . .9
Table 3. LPC11U3x/2x/1x memory configuration . . . . . .14
Table 4. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 5. Register overview: system control block (base
address 0x4004 8000) . . . . . . . . . . . . . . . . . .21
Table 6. Register overview: flash control block (base
address 0x4003 C000) . . . . . . . . . . . . . . . . . .22
Table 7. System memory remap register
(SYSMEMREMAP, address 0x4004 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 8. Peripheral reset control register (PRESETCTRL,
address 0x4004 8004) bit description. . . . . . . .23
Table 9. System PLL control register (SYSPLLCTRL,
address 0x4004 8008) bit description . . . . . . .24
Table 10. System PLL status register (SYSPLLSTAT,
address 0x4004 800C) bit description . . . . . . .24
Table 11. USB PLL control register (USBPLLCTRL, address
0x4004 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 12. USB PLL status register (USBPLLSTAT, address
0x4004 8014) bit description . . . . . . . . . . . . . .25
Table 13. System oscillator control register (SYSOSCCTRL,
address 0x4004 8020) bit description. . . . . . . .25
Table 14. Watchdog oscillator control register
(WDTOSCCTRL, address 0x4004 8024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 15. Internal resonant crystal control register
(IRCCTRL, address 0x4004 8028) bit description
27
Table 16. System reset status register (SYSRSTSTAT,
address 0x4004 8030) bit description. . . . . . . .27
Table 17. System PLL clock source select register
(SYSPLLCLKSEL, address 0x4004 8040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 18. System PLL clock source update enable register
(SYSPLLCLKUEN, address 0x4004 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 19. USB PLL clock source select register
(USBPLLCLKSEL, address 0x4004 8048) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 20. USB PLL clock source update enable register
(USBPLLCLKUEN, address 0x4004 804C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 21. Main clock source select register (MAINCLKSEL,
address 0x4004 8070) bit description. . . . . . . .30
Table 22. Main clock source update enable register
(MAINCLKUEN, address 0x4004 8074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 23. System clock divider register (SYSAHBCLKDIV,
address 0x4004 8078) bit description. . . . . . . .31
Table 24. System clock control register
(SYSAHBCLKCTRL, address 0x4004 8080) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 25. SSP0 clock divider register (SSP0CLKDIV,
address 0x4004 8094) bit description. . . . . . . .33
Table 26. USART clock divider register (UARTCLKDIV,
address 0x4004 8098) bit description . . . . . . . 33
Table 27. SPI1 clock divider register (SSP1CLKDIV,
address 0x4004 809C) bit description . . . . . . . 34
Table 28. USB clock source select register (USBCLKSEL,
address 0x4004 80C0) bit description . . . . . . . 34
Table 29. USB clock source update enable register
(USBCLKUEN, address 0x4004 80C4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 30. USB clock divider register (USBCLKDIV, address
0x4004 80C8) bit description . . . . . . . . . . . . . . 35
Table 31. CLKOUT clock source select register
(CLKOUTSEL, address 0x4004 80E0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 32. CLKOUT clock source update enable register
(CLKOUTUEN, address 0x4004 80E4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 33. CLKOUT clock divider registers (CLKOUTDIV,
address 0x4004 80E8) bit description . . . . . . . 36
Table 34. POR captured PIO status register 0
(PIOPORCAP0, address 0x4004 8100) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 35. POR captured PIO status register 1
(PIOPORCAP1, address 0x4004 8104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 36. BOD control register (BODCTRL, address 0x4004
8150) bit description. . . . . . . . . . . . . . . . . . . . . 37
Table 37. System tick timer calibration register
(SYSTCKCAL, address 0x4004 8154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 38. IRQ latency register (IRQLATENCY, address
0x4004 8170) bit description . . . . . . . . . . . . . . 38
Table 39. NMI source selection register (NMISRC, address
0x4004 8174) bit description . . . . . . . . . . . . . . 38
Table 40. Pin interrupt select registers (PINTSEL0 to 7,
address 0x4004 8178 to 0x4004 8194) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
T
a
ble 41. USB clock control register (USBCLKCTRL,
address 0x4004 8198) bit description . . . . . . . 39
Table 42. USB clock status register (USBCLKST, address
0x4004 819C) bit description . . . . . . . . . . . . . . 39
Table 43. Interrupt wake-up enable register 0 (STARTERP0,
address 0x4004 8204) bit description . . . . . . 40
Table 44. Interrupt wake-up enable register 1 (STARTERP1,
address 0x4004 8214) bit description . . . . . . 41
Table 45. Deep-sleep configuration register
(PDSLEEPCFG, address 0x4004 8230) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 46. Wake-up configuration register (PDAWAKECFG,
address 0x4004 8234) bit description . . . . . . 42
Table 47. Power configuration register (PDRUNCFG,
address 0x4004 8238) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 48. Device ID register (DEVICE_ID, address 0x4004
83F4) bit description . . . . . . . . . . . . . . . . . . . . 44
Table 49. Flash configuration register (FLASHCFG, address

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English