Xilinx Virtex-6 FPGA

206 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
RX_EYE_SCANMODE 2-bit
Binary
This attribute should be set to 00 for normal operation. Refer to RX Margin
Analysis, page 210 for detailed information.
RXPLL_DIVSEL_OUT Integer This divider defines the nominal line rate for the receiver. It can be set to 1,
2, or 4.
RX Line Rate = RX PLL Clock * 2/PLL_RXDIVSEL_OUT
Table 4-22: RX CDR Attributes (Cont’d)
Attribute Type Description
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