Xilinx Virtex-6 FPGA User Manual

248 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Table 4-49 defines the RX channel bonding attributes.
RXCHANREALIGN Out RXUSRCLK2 This signal from the RX elastic buffer is held High for at least
one cycle when the receiver has changed the alignment
between this transceiver and the master.
RXCHBONDI[3:0] In RXUSRCLK /
RXUSRCLK2
FPGA channel bonding control. This signal is used only by
slaves. It is driven from another transceiver’s RXCHBONDO
port that is the master in this configuration.
If GEN_RXUSRCLK is set to TRUE, the timing of
RXCHBONDI port is synchronous to RXUSRCLK2.
RXCHBONDO[3:0] Out RXUSRCLK /
RXUSRCLK2
FPGA channel bonding control. This signal is used by the
master and slaves to pass channel bonding and clock
correction control to other transceivers' RXCHBONDI ports.
If GEN_RXUSRCLK is set to TRUE, the timing of
RXCHBONDI port is synchronous to RXUSRCLK2.
RXCHBONDLEVEL[2:0] In RXUSRCLK2 Indicates the amount of internal pipelining used for the elastic
buffer control signals. A higher value permits more daisy-
chaining of RXCHBONDO and RXCHBONDI to ease
placement and routing constraints. To minimize required
latency through the RX elastic buffer, CHAN_BOND_LEVEL
in the master set to the smallest value possible for the required
amount of daisy-chaining.
See Connecting Channel Bonding Ports, page 251 for channel
bonding to learn how to set the channel bonding level.
RXCHBONDMASTER In RXUSRCLK2 Indicates that the transceiver is master for channel bonding. Its
RXCHBONDO port directly drives RXCHBONDI ports on one
or more SLAVE transceivers.
This port cannot be driven High at the same time as
RXCHBONDSLAVE.
RXCHBONDSLAVE In RXUSRCLK2 Indicates that this transceiver is a slave for channel bonding. Its
RXCHBONDI port is directly driven by the RXCHBONDO
port of another SLAVE or MASTER transceiver. If its
RXCHBONDLEVEL[2:0] setting is greater than 0, its
RXCHBONDO port may directly drive RXCHBONDI ports on
one or more other SLAVE transceivers.
This port cannot be driven High at the same time as
RXCHBONDMASTER.
RXENCHANSYNC In RXUSRCLK2 This port enables channel bonding (from the FPGA logic to
both the master and slaves).
Table 4-48: RX Channel Bonding Ports (Cont’d)
Port Dir Clock Domain Description
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English