Xilinx Virtex-6 FPGA

306 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Appendix B: DRP Address Map of the GTX Transceiver
13h
15:12
R/W
RX_SLIDE_AUTO_WAIT 3:0 0-15
1
(1)
11:10 CLK_COR_DET_LEN 1:0
1
00
2 01
Reserved
4
11
9:0 CLK_COR_SEQ_2_3 9:0 0-1023 1
(1)
14h
15
R/W
DEC_VALID_COMMA_ONLY
FALSE
0
TRUE 1
14 ALIGN_COMMA_WORD
1
0
2 1
13 RX_DECODE_SEQ_MATCH
FALSE
0
TRUE 1
12 Reserved
11 DEC_MCOMMA_DETECT
FALSE
0
TRUE 1
10 DEC_PCOMMA_DETECT
FALSE
0
TRUE 1
9:0 CLK_COR_SEQ_2_4 9:0 0-1023 1
(1)
15h
15:0 R/W PMA_CDR_SCAN 15:0
16h
15:11
R/W
CDR_PH_ADJ_TIME 4:0 0-31
1
(1)
10:0 PMA_CDR_SCAN 26:16
Table B-1: Attributes DRP Address Map (Cont’d)
DADDR
DRP Bits R/W Attribute Name Attribute Bits Attribute Encoding
DRP Binary
Encoding
www.BDTIC.com/XILINX