Xilinx Virtex-6 FPGA

308 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Appendix B: DRP Address Map of the GTX Transceiver
18h
15:4
R/W
Reserved 11:0
3RXGEARBOX_USE
FALSE
0
TRUE 1
2:0 GEARBOX_ENDEC 2:0 0-7 1
(1)
19h
15:0 R/W RXPLL_COM_CFG 15:0
1Ah
15:8
R/W
RXPLL_CP_CFG 7:0
7:0 RXPLL_COM_CFG 23:16
1Bh
15:14
R/W
RXPLL_DIVSEL_OUT 1:0
1
00
2 01
4 10
13:11 RXPLL_LKDET_CFG 2:0 0-7 1
(1)
10:7 Reserved 3:0
6 RXPLL_DIVSEL45_FB
5
1
4 0
5:1 RXPLL_DIVSEL_FB 4:0
2
00000
4 00010
5 00011
0 Reserved
1Ch
15
R/W
RX_OVERSAMPLE_MODE
FALSE
0
TRUE 1
14:6 Reserved 8:0
5:1 RXPLL_DIVSEL_REF 4:0
1
10000
2 00000
0 Reserved
1Dh
15:0 R/W TXPLL_COM_CFG 15:0
1Eh
15:8
R/W
TXPLL_CP_CFG 7:0
7:0 TXPLL_COM_CFG 23:16
1Fh
15:14
R/W
TXPLL_DIVSEL_OUT 1:0
1
00
2 01
4 10
13:11 TXPLL_LKDET_CFG 2:0 0-7 1
(1)
10:9 Reserved 1:0
8TX_CLK_SOURCE
RXPLL
1
TXPLL 0
7 Reserved
6 TXPLL_DIVSEL45_FB
5
1
4 0
5:1 TXPLL_DIVSEL_FB 4:0
2
00000
4 00010
5 00011
0 Reserved
Table B-1: Attributes DRP Address Map (Cont’d)
DADDR
DRP Bits R/W Attribute Name Attribute Bits Attribute Encoding
DRP Binary
Encoding
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