Xilinx Virtex-6 FPGA

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 309
UG366 (v2.5) January 17, 2011
20h
15
R/W
TX_OVERSAMPLE_MODE
FALSE
0
TRUE 1
14:6 Reserved 8:0
5:1 TXPLL_DIVSEL_REF 4:0
1
10000
2 00000
0 Reserved
21h
15
R/W
PCI_EXPRESS_MODE
FALSE
0
TRUE 1
14 Reserved
13:0 TX_DETECT_RX_CFG 13:0
22h
15 PMA_CAS_CLK_EN
FALSE
0
TRUE 1
14:0 Reserved 14:0
Table B-1: Attributes DRP Address Map (Cont’d)
DADDR
DRP Bits R/W Attribute Name Attribute Bits Attribute Encoding
DRP Binary
Encoding
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