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Xilinx Virtex-6 FPGA User Manual

Xilinx Virtex-6 FPGA
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Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 75
UG366 (v2.5) January 17, 2011
Implementation
X-Ref Target - Figure 1-38
Figure 1-38: Placement Diagram for the FF1155 Package (3 of 6)
HX255T:GTXE1_X1Y3
HX380T:GTXE1_X1Y3
HX255T:GTXE1_X1Y2
HX380T:GTXE1_X1Y2
HX255T:GTXE1_X1Y1
HX380T:GTXE1_X1Y1
HX255T:GTXE1_X1Y0
HX380T:GTXE1_X1Y0
QUAD_113
AH5
AH6
AL3
AL4
AJ3
AJ4
AM1
AM2
AJ8
AJ7
AL8
AL7
AK5
AK6
AN3
AN4
AM5
AM6
AP1
AP2
MGTTXP0_113
MGTTXN0_113
MGTRXP0_113
MGTRXN0_113
MGTTXP1_113
MGTTXN1_113
MGTRXP1_113
MGTRXN1_113
MGTREFCLK0P_113
MGTREFCLK0N_113
MGTREFCLK1P_113
MGTREFCLK1N_113
MGTTXP2_113
MGTTXN2_113
MGTRXP2_113
MGTRXN2_113
MGTTXP3_113
MGTTXN3_113
MGTRXP3_113
MGTRXN3_113
UG366_c1_38_111110
Right Edge of the Die
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Xilinx Virtex-6 FPGA Specifications

General IconGeneral
BrandXilinx
ModelVirtex-6 FPGA
CategoryTransceiver
LanguageEnglish

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