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Xilinx Virtex-6 FPGA User Manual

Xilinx Virtex-6 FPGA
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Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 81
UG366 (v2.5) January 17, 2011
Implementation
X-Ref Target - Figure 1-44
Figure 1-44: Placement Diagram for the FF1923 Package (3 of 10)
HX255T:GTXE1_X1Y3
HX380T:GTXE1_X1Y7
HX565T:GTXE1_X1Y7
HX255T:GTXE1_X1Y2
HX380T:GTXE1_X1Y6
HX565T:GTXE1_X1Y6
HX255T:GTXE1_X1Y1
HX380T:GTXE1_X1Y5
HX565T:GTXE1_X1Y5
HX255T:GTXE1_X1Y0
HX380T:GTXE1_X1Y4
HX565T:GTXE1_X1Y4
QUAD_113
AE7
AE8
AF1
AF2
AF5
AF6
AG3
AG4
AD10
AD9
AF10
AF9
AG7
AG8
AH1
AH2
AH5
AH6
AJ3
AJ4
UG366_c1_44_111110
MGTTXP0_113
MGTTXN0_113
MGTRXP0_113
MGTRXN0_113
MGTTXP1_113
MGTTXN1_113
MGTRXP1_113
MGTRXN1_113
MGTREFCLK0P_113
MGTREFCLK0N_113
MGTREFCLK1P_113
MGTREFCLK1N_113
MGTTXP2_113
MGTTXN2_113
MGTRXP2_113
MGTRXN2_113
MGTTXP3_113
MGTTXN3_113
MGTRXP3_113
MGTRXN3_113
Right Edge of the Die
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Xilinx Virtex-6 FPGA Specifications

General IconGeneral
BrandXilinx
ModelVirtex-6 FPGA
CategoryTransceiver
LanguageEnglish

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