Altera Stratix - Page 135

Altera Corporation Section III–3
I/O Standards
5 July 2005, v3.2 Updated Table 5–14 on page 5–58.
September 2004,
v3.1
● Updated Note 3 in Table 5–10 on page 5–54.
● Updated Table 5–7 on page 5–34.
● Updated Table 5–8 on page 5–36.
● Updated description of “R
D
Differential Termination” on
page 5–46.
● Updated Note 5 in Table 5–14 on page 5–58.
● Updated Notes 2, 5, and 7 in Table 5–11 on page 5–56
through Table 5–14 on page 5–58.
● Added new text about spanning two I/O banks on
page 5–60.
April 2004, v3.0
● Updated notes for Figure 5–17.
● Updated Table 5–7, 5–8, and 5–10.
● “Data Alignment with Clock” section, last sentence: change
made from 90 degrees to 180 degrees.
November 2003,
v2.2
● Removed support for series and parallel on-chip
termination.
● Updated the number of channels per PLL in Tables 5-10
through 5-14.
October 2003,
v2.1
● Added -8 speed grade device information, including Tables
5-7 and 5-8.
July 2003, v2.0
● Format changes throughout Chapter.
● Relaxed restriction of input pins next to differential pins for
flip chip packages in Figure 5-1, Note 5.
● Wire bond package performance specification for “high”
speed channels was increased to 624 Mbps from 462 Mbps
throughout Chapter.
● Updated high-speed I/O specification for J=2 in Tables 5-7
and 5-8.
● Updated Tables 5-10 to 5-14 to reflect PLL cross-bank
support for high-speed differential channels at full speed.
● Increased maximum output clock frequency to 462 to 500
MHz on page 5-66.
Chapter Date/Version Changes Made Comments