UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 345 of 523
NXP Semiconductors
UM10462
Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input cannot exceed one half of the
PCLK clock. Consequently, the duration of the HIGH/LOW levels on the same CAP input
in this case can not be shorter than 1/PCLK.
Bits 7:4 of this register are also used to enable and configure the capture-clears-timer
feature. This feature allows for a designated edge on a particular CAP input to reset the
timer to all zeros. Using this mechanism to clear the timer on the leading edge of an input
pulse and performing a capture on the trailing edge, permits direct pulse-width
measurement using a single capture input without the need to perform a subtraction
operation in software.
Remark: The bit positions for the CAP1 channel count input select (CIS) and edge select
bits (SELCC) are different for counter/timers CT16B0 (Table 312
) and CT16B1
(Table 313
).
Table 312. Count Control Register (CTCR, address 0x4000 C070 (CT16B0)) bit description
Bit Symbol Value Description Reset
value
1:0 CTM Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or
clear PC and increment Timer Counter (TC).
Remark: If Counter mode is selected in the CTCR, bits 2:0
in the Capture Control Register (CCR) must be programmed
as 000.
0
0x0 Timer Mode: every rising PCLK edge
0x1 Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
0x2 Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
0x3 Counter Mode: TC is incremented on both edges on the
CAP input selected by bits 3:2.
3:2 CIS Count Input Select. In counter mode (when bits 1:0 in this
register are not 00), these bits select which CAP pin is
sampled for clocking. Values 0x1 and 0x3 are reserved.
0
0x0 CT16B0_CAP0.
0x1 Reserved.
0x2 CT16B0_CAP1.
4 ENCC Setting this bit to 1 enables clearing of the timer and the
prescaler when the capture-edge event specified in bits 7:5
occurs.
0
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