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NXP Semiconductors LPC11U3x

NXP Semiconductors LPC11U3x
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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 447 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
The vector table is fixed at address
0x00000000
.
24.3.3.5 Exception priorities
As Table 24–421 shows, all exceptions have an associated priority, with:
a lower priority value indicating a higher priority
configurable priorities for all exceptions except Reset, HardFault, and NMI.
If software does not configure any priorities, then all exceptions with a configurable priority
have a priority of 0. For information about configuring exception priorities see
Section 24–24.5.3.7
Section 24–24.5.2.6.
Configurable priority values are in the range 0-192, in steps of 64. The Reset, HardFault,
and NMI exceptions, with fixed negative priority values, always have higher priority than
any other exception.
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