UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 488 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.5.2.6 Interrupt Priority Registers
The IPR0-IPR7 registers provide an 2-bit priority field for each interrupt. These registers
are only word-accessible. See the register summary in Table 24–434
for their attributes.
Each register holds four priority fields as shown:
See Section 24–24.5.2.1 for more information about the access to the interrupt priority
array, which provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt M as follows:
• the corresponding IPR number, N, is given by N = N DIV 4
• the byte offset of the required Priority field in this register is M MOD 4, where:
– byte offset 0 refers to register bits[7:0]
– byte offset 1 refers to register bits[15:8]
– byte offset 2 refers to register bits[23:16]
– byte offset 3 refers to register bits[31:24].
24.5.2.7 Level-sensitive and pulse interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also
described as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt
signal. Typically this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
Fig 86. IPR register
35,B
       
35,B 35,B 35,B
,35
35,BQ 35,BQ 35,BQ 35,BQ
,35Q
35,B 35,B 35,B 35,B
,35
 
 
Table 440. IPR bit assignments
Bits Name Function
[31:24] Priority, byte offset 3 Each priority field holds a priority value, 0-3. The lower the
value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:6] of each field, bits
[5:0] read as zero and ignore writes.
[23:16] Priority, byte offset 2
[15:8] Priority, byte offset 1
[7:0] Priority, byte offset 0
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