UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 487 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.5.2.4 Interrupt Set-pending Register
The ISPR forces interrupts into the pending state, and shows which interrupts are
pending. See the register summary in Table 24–434
for the register attributes.
The bit assignments are:
Remark: Writing 1 to the ISPR bit corresponding to:
• an interrupt that is pending has no effect
• a disabled interrupt sets the state of that interrupt to pending.
24.5.2.5 Interrupt Clear-pending Register
The ICPR removes the pending state from interrupts, and shows which interrupts are
pending. See the register summary in Table 24–434
for the register attributes.
The bit assignments are:
Remark: Writing 1 to an ICPR bit does not affect the active state of the corresponding
interrupt.
Table 437. ICER bit assignments
Bits Name Function
[31:0] CLRENA Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Table 438. ISPR bit assignments
Bits Name Function
[31:0] SETPEND Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
Table 439. ICPR bit assignments
Bits Name Function
[31:0] CLRPEND Interrupt clear-pending bits.
Write:
0 = no effect
1 = removes pending state an interrupt.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
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