UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 470 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
BICS {Rd,} Rn, Rm
where:
Rd is the destination register.
Rn is the register holding the first operand and is the same as the destination register.
Rm second register.
24.4.5.2.2 Operation
The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and inclusive
OR operations on the values in Rn and Rm.
The BIC instruction performs an AND operation on the bits in Rn with the logical negation
of the corresponding bits in the value of Rm.
The condition code flags are updated on the result of the operation, see
Section 24.4.3.6.1
.
24.4.5.2.3 Restrictions
In these instructions, Rd, Rn, and Rm must only specify R0-R7.
24.4.5.2.4 Condition flags
These instructions:
• update the N and Z flags according to the result
• do not affect the C or V flag.
24.4.5.2.5 Examples
ANDS R2, R2, R1
ORRS R2, R2, R5
ANDS R5, R5, R8
EORS R7, R7, R6
BICS R0, R0, R1
24.4.5.3 ASR, LSL, LSR, and ROR
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.
24.4.5.3.1 Syntax
ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs
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