UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 472 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
where:
Rn is the register holding the first operand.
Rm is the register to compare with.
imm is the immediate value to compare with.
24.4.5.4.2 Operation
These instructions compare the value in a register with either the value in another register
or an immediate value. They update the condition flags on the result, but do not write the
result to a register.
The CMP instruction subtracts either the value in the register specified by Rm, or the
immediate imm from the value in Rn and updates the flags. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Rm to the value in Rn and updates the flags. This
is the same as an ADDS instruction, except that the result is discarded.
24.4.5.4.3 Restrictions
For the:
• CMN
instruction Rn, and Rm must only specify R0-R7.
• CMP instruction:
– Rn and Rm can specify R0-R14
– immediate must be in the range 0-255.
24.4.5.4.4 Condition flags
These instructions update the N, Z, C and V flags according to the result.
24.4.5.4.5 Examples
CMP R2, R9
CMN R0, R2
24.4.5.5 MOV and MVN
Move and Move NOT.
24.4.5.5.1 Syntax
MOV{S} Rd, Rm
MOVS Rd, #imm
MVNS Rd, Rm
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see Section 24–24.4.3.6
.
Rd is the destination register.
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