UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 474 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.5.6.2 Operation
The MUL instruction multiplies the values in the registers specified by Rn and Rm, and
places the least significant 32 bits of the result in Rd. The condition code flags are
updated on the result of the operation, see Section 24–24.4.3.6
.
The results of this instruction does not depend on whether the operands are signed or
unsigned.
24.4.5.6.3 Restrictions
In this instruction:
• Rd, Rn, and Rm must only specify R0-R7
• Rd must be the same as Rm.
24.4.5.6.4 Condition flags
This instruction:
• updates the N and Z flags according to the result
• does not affect the C or V flags.
24.4.5.6.5 Examples
MULS R0, R2, R0 ; Multiply with flag update, R0 = R0 x R2
24.4.5.7 REV, REV16, and REVSH
Reverse bytes.
24.4.5.7.1 Syntax
REV Rd, Rn
REV16 Rd, Rn
REVSH Rd, Rn
where:
Rd is the destination register.
Rn is the source register.
24.4.5.7.2 Operation
Use these instructions to change endianness of data:
REV — converts 32-bit big-endian data into little-endian data or 32-bit little-endian data
into big-endian data.
REV16 — converts two packed 16-bit big-endian data into little-endian data or two packed
16-bit little-endian data into big-endian data.
REVSH — converts 16-bit signed big-endian data into 32-bit signed little-endian data or
16-bit signed little-endian data into 32-bit signed big-endian data.
24.4.5.7.3 Restrictions
In these instructions, Rd, and Rn must only specify R0-R7.
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