UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 475 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.5.7.4 Condition flags
These instructions do not change the flags.
24.4.5.7.5 Examples
REV R3, R7 ; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5 ; Reverse signed halfword
24.4.5.8 SXT and UXT
Sign extend and Zero extend.
24.4.5.8.1 Syntax
SXTB Rd, Rm
SXTH Rd, Rm
UXTB Rd, Rm
UXTH Rd, Rm
where:
Rd is the destination register.
Rm is the register holding the value to be extended.
24.4.5.8.2 Operation
These instructions extract bits from the resulting value:
• SXTB extracts bits[7:0] and sign extends to 32 bits
• UXTB extracts bits[7:0] and zero extends to 32 bits
• SXTH extracts bits[15:0] and sign extends to 32 bits
• UXTH extracts bits[15:0] and zero extends to 32 bits.
24.4.5.8.3 Restrictions
In these instructions, Rd and Rm must only specify R0-R7.
24.4.5.8.4 Condition flags
These instructions do not affect the flags.
24.4.5.8.5 Examples
SXTH R4, R6 ; Obtain the lower halfword of the
; value in R6 and then sign extend to
; 32 bits and write the result to R4.
UXTB R3, R1 ; Extract lowest byte of the value in R10 and zero
; extend it, and write the result to R3
24.4.5.9 TST
Test bits.
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