UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 476 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.5.9.1 Syntax
TST Rn, Rm
where:
Rn is the register holding the first operand.
Rm the register to test against.
24.4.5.9.2 Operation
This instruction tests the value in a register against another register. It updates the
condition flags based on the result, but does not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value in
Rm. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with a register that has that bit
set to 1 and all other bits cleared to 0.
24.4.5.9.3 Restrictions
In these instructions, Rn and Rm must only specify R0-R7.
24.4.5.9.4 Condition flags
This instruction:
• updates the N and Z flags according to the result
• does not affect the C or V flags.
24.4.5.9.5 Examples
TST R0, R1 ; Perform bitwise AND of R0 value and R1 value,
; condition code flags are updated but result is discarded
24.4.6 Branch and control instructions
Table 430 shows the branch and control instructions:
24.4.6.1 B, BL, BX, and BLX
Branch instructions.
24.4.6.1.1 Syntax
B{cond} label
BL label
Table 430. Branch and control instructions
Mnemonic Brief description See
B{cc} Branch {conditionally} Section 24–24.4.6.1
BL Branch with Link Section 24–24.4.6.1
BLX Branch indirect with Link Section 24–24.4.6.1
BX Branch indirect Section 24–24.4.6.1
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