UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 477 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
BX Rm
BLX Rm
where:
cond is an optional condition code, see Section 24–24.4.3.6
.
label is a PC-relative expression. See Section 24–24.4.3.5
.
Rm is a register providing the address to branch to.
24.4.6.1.2 Operation
All these instructions cause a branch to the address indicated by label or contained in the
register specified by Rm. In addition:
• The BL and BLX instructions write the address of the next instruction to LR, the link
register R14.
• The BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.
BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is
suitable for use by a subsequent POP {PC} or BX instruction to perform a successful
return branch.
Table 431
shows the ranges for the various branch instructions.
24.4.6.1.3 Restrictions
In these instructions:
• Do not use SP or PC in the BX or BLX instruction.
• For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update
the EPSR T-bit and is discarded from the target address.
Remark: Bcond is the only conditional instruction on the Cortex-M0 processor.
24.4.6.1.4 Condition flags
These instructions do not change the flags.
24.4.6.1.5 Examples
B loopA ; Branch to loopA
BL funC ; Branch with link (Call) to function funC, return address
; stored in LR
Table 431. Branch ranges
Instruction Branch range
B label ï€2 KB to +2 KB
Bcond label ï€256 bytes to +254 bytes
BL label ï€16 MB to +16 MB
BX Rm Any value in register
BLX Rm Any value in register
To Next Page
Loading...
Need help?
General
