NXP Semiconductors LPC11U3x

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 478 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
BX LR ; Return from function call
BLX R0 ; Branch with link and exchange (Call) to a address stored
; in R0
BEQ labelD ; Conditionally branch to labelD if last flag setting
; instruction set the Z flag, else do not branch.
24.4.7 Miscellaneous instructions
Table 432 shows the remaining Cortex-M0 instructions:
24.4.7.1 BKPT
Breakpoint.
24.4.7.1.1 Syntax
BKPT #imm
where:
imm is an integer in the range 0-255.
Table 432. Miscellaneous instructions
Mnemonic Brief description See
BKPT Breakpoint Section 24–24.4.7.
1
CPSID Change Processor State, Disable Interrupts Section 24–24.4.7.
2
CPSIE Change Processor State, Enable Interrupts Section 24–24.4.7.
2
DMB Data Memory Barrier Section 24–24.4.7.
3
DSB Data Synchronization Barrier Section 24–24.4.7.
4
ISB Instruction Synchronization Barrier Section 24–24.4.7.
5
MRS Move from special register to register Section 24–24.4.7.
6
MSR Move from register to special register Section 24–24.4.7.
7
NOP No Operation Section 24–24.4.7.
8
SEV Send Event Section 24–24.4.7.
9
SVC Supervisor Call Section 24–24.4.7.
10
WFE Wait For Event Section 24–24.4.7.
11
WFI Wait For Interrupt Section 24–24.4.7.
12