UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 493 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
[1] This is the same value as IPSR bits[5:0], see Table 24–416.
When you write to the ICSR, the effect is Unpredictable if you:
• write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
• write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
24.5.3.4 Application Interrupt and Reset Control Register
The AIRCR provides endian status for data accesses and reset control of the system. See
the register summary in Table 24–442
and Table 24–445 for its attributes.
To write to this register, you must write
0x05FA
to the VECTKEY field, otherwise the
processor ignores the write.
The bit assignments are:
[22] ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
[21:18] - - Reserved.
[17:12] VECTPENDING RO Indicates the exception number of the highest priority
pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
[11:6] - - Reserved.
[5:0] VECTACTIVE
[1]
RO Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
[1]
of the currently
active exception.
Remark: Subtract 16 from this value to obtain the
CMSIS IRQ number that identifies the corresponding bit
in the Interrupt Clear-Enable, Set-Enable,
Clear-Pending, Set-pending, and Priority Register, see
Table 24–416
.
Table 444. ICSR bit assignments
Bits Name Type Function
Table 445. AIRCR bit assignments
Bits Name Type Function
[31:16] Read: Reserved
Write: VECTKEY
RW Register key:
Reads as Unknown
On writes, write
0x05FA
to VECTKEY, otherwise the
write is ignored.
[15] ENDIANESS RO Data endianness implemented:
0 = Little-endian
1 = Big-endian.
[14:3] - - Reserved
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