UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 513 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
25.6 Contents
Chapter 1: LPC11U3x/2x/1x Introductory information
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Ordering information . . . . . . . . . . . . . . . . . . . . 8
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: LPC11U3x/2x/1x Memory mapping
2.1 How to read this chapter. . . . . . . . . . . . . . . . . 14 2.2 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 3: LPC11U3x/2x/1x System control block
3.1 How to read this chapter. . . . . . . . . . . . . . . . . 19
3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Clocking and power control . . . . . . . . . . . . . . 19
3.5 Register description . . . . . . . . . . . . . . . . . . . . 20
3.5.1 System memory remap register . . . . . . . . . . . 22
3.5.2 Peripheral reset control register . . . . . . . . . . . 23
3.5.3 System PLL control register . . . . . . . . . . . . . . 23
3.5.4 System PLL status register. . . . . . . . . . . . . . . 24
3.5.5 USB PLL control register . . . . . . . . . . . . . . . . 24
3.5.6 USB PLL status register . . . . . . . . . . . . . . . . . 25
3.5.7 System oscillator control register . . . . . . . . . . 25
3.5.8 Watchdog oscillator control register . . . . . . . . 26
3.5.9 Internal resonant crystal control register. . . . . 27
3.5.10 System reset status register. . . . . . . . . . . . . . 27
3.5.11 System PLL clock source select register . . . . 27
3.5.12 System PLL clock source update register . . . 29
3.5.13 USB PLL clock source select register. . . . . . . 29
3.5.14 USB PLL clock source update enable register 29
3.5.15 Main clock source select register . . . . . . . . . . 30
3.5.16 Main clock source update enable register . . . 30
3.5.17 System clock divider register . . . . . . . . . . . . . 30
3.5.18 System clock control register . . . . . . . . . . . . . 31
3.5.19 SSP0 clock divider register. . . . . . . . . . . . . . . 33
3.5.20 USART clock divider register . . . . . . . . . . . . . 33
3.5.21 SSP1 clock divider register. . . . . . . . . . . . . . . 34
3.5.22 USB clock source select register . . . . . . . . . . 34
3.5.23 USB clock source update enable register. . . . 34
3.5.24 USB clock divider register. . . . . . . . . . . . . . . . 35
3.5.25 CLKOUT clock source select register. . . . . . . 35
3.5.26 CLKOUT clock source update enable register 35
3.5.27 CLKOUT clock divider register . . . . . . . . . . . . 36
3.5.28 POR captured PIO status register 0. . . . . . . . 36
3.5.29 POR captured PIO status register 1. . . . . . . . 36
3.5.30 BOD control register. . . . . . . . . . . . . . . . . . . . 36
3.5.31 System tick counter calibration register . . . . . 37
3.5.32 IRQ latency register . . . . . . . . . . . . . . . . . . . . 37
3.5.33 NMI source selection register. . . . . . . . . . . . . 38
3.5.34 Pin interrupt select registers. . . . . . . . . . . . . . 38
3.5.35 USB clock control register . . . . . . . . . . . . . . . 39
3.5.36 USB clock status register . . . . . . . . . . . . . . . . 39
3.5.37 Interrupt wake-up enable register 0 . . . . . . . . 40
3.5.38 Interrupt wake-up enable register 1 . . . . . . . . 40
3.5.39 Deep-sleep mode configuration register. . . . . 41
3.5.40 Wake-up configuration register . . . . . . . . . . . 42
3.5.41 Power configuration register . . . . . . . . . . . . . 43
3.5.42 Device ID register . . . . . . . . . . . . . . . . . . . . . 44
3.5.43 Flash memory access . . . . . . . . . . . . . . . . . . 45
3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7 Start-up behavior. . . . . . . . . . . . . . . . . . . . . . . 46
3.8 Brown-out detection . . . . . . . . . . . . . . . . . . . . 46
3.9 Power management . . . . . . . . . . . . . . . . . . . . 47
3.9.1 Reduced power modes and WWDT lock
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.9.2 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.9.2.1 Power configuration in Active mode. . . . . . . . 48
3.9.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.9.3.1 Power configuration in Sleep mode . . . . . . . . 48
3.9.3.2 Programming Sleep mode . . . . . . . . . . . . . . . 48
3.9.3.3 Wake-up from Sleep mode . . . . . . . . . . . . . . 49
3.9.4 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 49
3.9.4.1 Power configuration in Deep-sleep mode . . . 49
3.9.4.2 Programming Deep-sleep mode . . . . . . . . . . 49
3.9.4.3 Wake-up from Deep-sleep mode . . . . . . . . . . 50
3.9.5 Power-down mode. . . . . . . . . . . . . . . . . . . . . 50
3.9.5.1 Power configuration in Power-down mode . . 51
3.9.5.2 Programming Power-down mode . . . . . . . . . 51
3.9.5.3 Wake-up from Power-down mode . . . . . . . . . 51
3.9.6 Deep power-down mode . . . . . . . . . . . . . . . . 52
3.9.6.1 Power configuration in Deep power-down
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.9.6.2 Programming Deep power-down mode . . . . . 52
3.9.6.3 Wake-up from Deep power-down mode . . . . 53
3.10 System PLL/USB PLL functional description 53
3.10.1 Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.10.2 Power-down control . . . . . . . . . . . . . . . . . . . . 54
3.10.3 Divider ratio programming . . . . . . . . . . . . . . . 54
Post divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Feedback divider . . . . . . . . . . . . . . . . . . . . . . . 54
Changing the divider values. . . . . . . . . . . . . . . 54
3.10.4 Frequency selection. . . . . . . . . . . . . . . . . . . . 55
3.10.4.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.10.4.2 Power-down mode. . . . . . . . . . . . . . . . . . . . . 55
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