UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 512 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
25.5 Figures
Fig 1. Block diagram (LPC11U1x) . . . . . . . . . . . . . . . . .11
Fig 2. Block diagram (LPC11U2x) . . . . . . . . . . . . . . . . .12
Fig 3. Block diagram (LPC11U3x) . . . . . . . . . . . . . . . . .13
Fig 4. LPC11U1x memory map . . . . . . . . . . . . . . . . . . .16
Fig 5. LPC11U2x memory map . . . . . . . . . . . . . . . . . . .17
Fig 6. LPC11U3x memory map . . . . . . . . . . . . . . . . . . .18
Fig 7. LPC11U3x/2x/1x CGU block diagram . . . . . . . . .20
Fig 8. Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Fig 9. System PLL block diagram . . . . . . . . . . . . . . . . .53
Fig 10. Power profiles pointer structure. . . . . . . . . . . . . .60
Fig 11. LPC11U3x/2x/1x clock configuration for power API
use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Fig 12. Power profiles usage . . . . . . . . . . . . . . . . . . . . . .65
Fig 13. Standard I/O pin configuration . . . . . . . . . . . . . . .81
Fig 14. Reset pad configuration. . . . . . . . . . . . . . . . . . . .83
Fig 15. Pin configuration (HVQFN33) . . . . . . . . . . . . . .129
Fig 16. Pin configuration (LQFP48) . . . . . . . . . . . . . . . .130
Fig 17. Pin configuration (TFBGA48) . . . . . . . . . . . . . .131
Fig 18. Pin configuration (LQFP64) . . . . . . . . . . . . . . . .131
Fig 19. USB device driver pointer structure. . . . . . . . . .172
Fig 20. USB block diagram . . . . . . . . . . . . . . . . . . . . . .222
Fig 21. USB software interface . . . . . . . . . . . . . . . . . . .223
Fig 22. Endpoint command/status list (see also Table 227
).
234
Fig 23. Flowchart of control endpoint 0 - OUT direction 237
Fig 24. Flowchart of control endpoint 0 - IN direction . .238
Fig 25. Auto-RTS Functional Timing . . . . . . . . . . . . . . .252
Fig 26. Auto-CTS Functional Timing . . . . . . . . . . . . . . .253
Fig 27. Auto-baud a) mode 0 and b) mode 1 waveform 258
Fig 28. Algorithm for setting USART dividers . . . . . . . .262
Fig 29. Typical smart card application . . . . . . . . . . . . . .272
Fig 30. Smart card T = 0 waveform . . . . . . . . . . . . . . . .272
Fig 31. USART block diagram . . . . . . . . . . . . . . . . . . . .274
Fig 32. Texas Instruments Synchronous Serial Frame
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer. . . . . . . . . . . . . . . . . . . . .283
Fig 33. SPI frame format with CPOL=0 and CPHA=0 (a)
Single and b) Continuous Transfer). . . . . . . . . .284
Fig 34. SPI frame format with CPOL=0 and CPHA=1 . .285
Fig 35. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Single and b) Continuous Transfer). . . . . . . . . .286
Fig 36. SPI Frame Format with CPOL = 1 and CPHA = 1. .
287
Fig 37. Microwire frame format (single transfer) . . . . . .288
Fig 38. Microwire frame format (continuous transfers) .288
Fig 39. Microwire frame format setup and hold details .289
Fig 40. I
2
C-bus configuration . . . . . . . . . . . . . . . . . . . . .291
Fig 41. I
2
C serial interface block diagram . . . . . . . . . . .301
Fig 42. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .303
Fig 43. Serial clock synchronization. . . . . . . . . . . . . . . .303
Fig 44. Format in the Master Transmitter mode. . . . . . .305
Fig 45. Format of Master Receiver mode . . . . . . . . . . .306
Fig 46. A Master Receiver switches to Master Transmitter
after sending Repeated START. . . . . . . . . . . . .306
Fig 47. Format of Slave Receiver mode . . . . . . . . . . . .307
Fig 48. Format of Slave Transmitter mode . . . . . . . . . .307
Fig 49. Format and states in the Master Transmitter mode
311
Fig 50. Format and states in the Master Receiver mode . .
314
Fig 51. Format and states in the Slave Receiver mode 318
Fig 52. Format and states in the Slave Transmitter mode .
321
Fig 53. Simultaneous Repeated START conditions from two
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Fig 54. Forced access to a busy I
2
C-bus . . . . . . . . . . . 323
Fig 55. Recovering from a bus obstruction caused by a
LOW level on SDA . . . . . . . . . . . . . . . . . . . . . . 324
Fig 56. Sample PWM waveforms with a PWM cycle length
of 100 (selected by MR2) and MAT2:0 enabled as
PWM outputs by the PWMC register. . . . . . . . . 348
Fig 57. A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . . 349
Fig 58. A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . 349
Fig 59. 16-bit counter/timer block diagram . . . . . . . . . . 350
Fig 60. Sample PWM waveforms with a PWM cycle length
of 100 (selected by MR2) and MAT2:0 enabled as
PWM outputs by the PWMC register. . . . . . . . . 366
Fig 61. A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . . 366
Fig 62. A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . 367
Fig 63. 32-bit counter/timer block diagram . . . . . . . . . . 368
Fig 64. Watchdog block diagram. . . . . . . . . . . . . . . . . . 371
Fig 65. Early Watchdog Feed with Windowed Mode
Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Fig 66. Correct Watchdog Feed with Windowed Mode
Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Fig 67. Watchdog Warning Interrupt . . . . . . . . . . . . . . . 378
Fig 68. System tick timer block diagram . . . . . . . . . . . . 379
Fig 69. Boot process flowchart . . . . . . . . . . . . . . . . . . . 396
Fig 70. IAP parameter passing . . . . . . . . . . . . . . . . . . . 412
Fig 71. Algorithm for generating a 128-bit signature. . . 423
Fig 72. Connecting the SWD pins to a standard SWD
connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Fig 73. ROM pointer structure. . . . . . . . . . . . . . . . . . . . 427
Fig 74. Cortex-M0 implementation . . . . . . . . . . . . . . . . 432
Fig 75. Processor core register set . . . . . . . . . . . . . . . . 435
Fig 76. APSR, IPSR, EPSR register bit assignments . 436
Fig 77. Cortex-M0 memory map . . . . . . . . . . . . . . . . . . 441
Fig 78. Memory ordering restrictions. . . . . . . . . . . . . . . 442
Fig 79. Little-endian format . . . . . . . . . . . . . . . . . . . . . . 444
Fig 80. Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Fig 81. Exception entry stack contents . . . . . . . . . . . . . 449
Fig 82. ASR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Fig 83. LSR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Fig 84. LSL #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Fig 85. ROR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Fig 86. IPR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
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