UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 511 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
Table 409. Flash module status clear register (FMSTATCLR
- 0x0x4003 CFE8) bit description . . . . . . . . . .422
Table 410. Serial Wire Debug pin description . . . . . . . . .424
Table 411. JTAG boundary scan pin description . . . . . . .425
Table 412. Summary of processor mode and stack use
options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .434
Table 413. Core register set summary. . . . . . . . . . . . . . .435
Table 414. PSR register combinations . . . . . . . . . . . . . .436
Table 415. APSR bit assignments . . . . . . . . . . . . . . . . . .437
Table 416. IPSR bit assignments. . . . . . . . . . . . . . . . . . .437
Table 417. EPSR bit assignments . . . . . . . . . . . . . . . . . .438
Table 418. PRIMASK register bit assignments . . . . . . . .438
Table 419. CONTROL register bit assignments . . . . . . .439
Table 420. Memory access behavior. . . . . . . . . . . . . . . .443
Table 421. Properties of different exception types. . . . . .445
Table 422. Exception return behavior . . . . . . . . . . . . . . .450
Table 423. Cortex-M0 instructions. . . . . . . . . . . . . . . . . .453
Table 424. CMSIS intrinsic functions to generate some
Cortex-M0 instructions . . . . . . . . . . . . . . . . . .455
Table 425. insic functions to access the special registers . .
456
Table 426. Condition code suffixes . . . . . . . . . . . . . . . . .460
Table 427. Access instructions . . . . . . . . . . . . . . . . . . . .461
Table 428. Data processing instructions . . . . . . . . . . . . .467
Table 429. ADC, ADD, RSB, SBC and SUB operand
restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . .469
Table 430. Branch and control instructions . . . . . . . . . . .476
Table 431. Branch ranges . . . . . . . . . . . . . . . . . . . . . . . .477
Table 432. Miscellaneous instructions. . . . . . . . . . . . . . .478
Table 433. Core peripheral register regions . . . . . . . . . .485
Table 434. NVIC register summary . . . . . . . . . . . . . . . . .485
Table 435. CMISIS acess NVIC functions . . . . . . . . . . .486
Table 436. ISER bit assignments. . . . . . . . . . . . . . . . . . .486
Table 437. ICER bit assignments . . . . . . . . . . . . . . . . . .487
Table 438. ISPR bit assignments. . . . . . . . . . . . . . . . . . .487
Table 439. ICPR bit assignments . . . . . . . . . . . . . . . . . .487
Table 440. IPR bit assignments. . . . . . . . . . . . . . . . . . . .488
Table 441. CMSIS functions for NVIC control . . . . . . . . .490
Table 442. Summary of the SCB registers . . . . . . . . . . .490
Table 443. CPUID register bit assignments. . . . . . . . . . .491
Table 444. ICSR bit assignments . . . . . . . . . . . . . . . . . .492
Table 445. AIRCR bit assignments . . . . . . . . . . . . . . . . .493
Table 446. SCR bit assignments . . . . . . . . . . . . . . . . . . .494
Table 447. CCR bit assignments . . . . . . . . . . . . . . . . . . .495
Table 448. System fault handler priority fields. . . . . . . . .495
Table 449. SHPR2 register bit assignments . . . . . . . . . .495
Table 450. SHPR3 register bit assignments . . . . . . . . . .496
Table 451. System timer registers summary . . . . . . . . . .496
Table 452. SYST_CSR bit assignments . . . . . . . . . . . . .496
Table 453. SYST_RVR bit assignments . . . . . . . . . . . . .497
Table 454. SYST_CVR bit assignments . . . . . . . . . . . . .497
Table 455. SYST_CALIB register bit assignments . . . . .498
Table 456. Cortex M0- instruction summary . . . . . . . . . .498
Table 457. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .502
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