UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 467 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.4.6.5 Examples
PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack
PUSH {R2,LR} ; Push R2 and the link-register onto the stack
POP {R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to
; the new PC.
24.4.5 General data processing instructions
Table 428 shows the data processing instructions:
24.4.5.1 ADC, ADD, RSB, SBC, and SUB
Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.
24.4.5.1.1 Syntax
ADCS {Rd,} Rn, Rm
Table 428. Data processing instructions
Mnemonic Brief description See
ADCS Add with Carry Section 24–24.4.5.1
ADD{S} Add Section 24–24.4.5.1
ANDS Logical AND Section 24–24.4.5.2
ASRS Arithmetic Shift Right Section 24–24.4.5.3
BICS Bit Clear Section 24–24.4.5.2
CMN Compare Negative Section 24–24.4.5.4
CMP Compare Section 24–24.4.5.4
EORS Exclusive OR Section 24–24.4.5.2
LSLS Logical Shift Left Section 24–24.4.5.3
LSRS Logical Shift Right Section 24–24.4.5.3
MOV{S} Move Section 24–24.4.5.5
MULS Multiply Section 24–24.4.5.6
MVNS Move NOT Section 24–24.4.5.5
ORRS Logical OR Section 24–24.4.5.2
REV Reverse byte order in a word Section 24–24.4.5.7
REV16 Reverse byte order in each halfword Section 24–24.4.5.7
REVSH Reverse byte order in bottom halfword
and sign extend
Section 24–24.4.5.7
RORS Rotate Right Section 24–24.4.5.3
RSBS Reverse Subtract Section 24–24.4.5.1
SBCS Subtract with Carry Section 24–24.4.5.1
SUBS Subtract Section 24–24.4.5.1
SXTB Sign extend a byte Section 24–24.4.5.8
SXTH Sign extend a halfword Section 24–24.4.5.8
UXTB Zero extend a byte Section 24–24.4.5.8
UXTH Zero extend a halfword Section 24–24.4.5.8
TST Test Section 24–24.4.5.9
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