UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 455 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.2 Intrinsic functions
ISO/IEC C code cannot directly access some Cortex-M0 instructions. This section
describes intrinsic functions that can generate these instructions, provided by the CMSIS
and that might be provided by a C compiler. If a C compiler does not support an
appropriate intrinsic function, you might have to use inline assembler to access the
relevant instruction.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC
C code cannot directly access:
STR Rt, [Rn, <Rm|#imm>] Store Register as word - Section 24–24.4.4
STRB Rt, [Rn, <Rm|#imm>] Store Register as byte - Section 24–24.4.4
STRH Rt, [Rn, <Rm|#imm>] Store Register as halfword - Section 24–24.4.4
SUB{S} {Rd,} Rn,
<Rm|#imm>
Subtract N,Z,C,V Section 24–24.4.5
.1
SVC #imm Supervisor Call - Section 24–24.4.7
.10
SXTB Rd, Rm Sign extend byte - Section 24–24.4.5
.8
SXTH Rd, Rm Sign extend halfword - Section 24–24.4.5
.8
TST Rn, Rm Logical AND based test N,Z Section 24–24.4.5
.9
UXTB Rd, Rm Zero extend a byte - Section 24–24.4.5
.8
UXTH Rd, Rm Zero extend a halfword - Section 24–24.4.5
.8
WFE - Wait For Event - Section 24–24.4.7
.11
WFI - Wait For Interrupt - Section 24–24.4.7
.12
Table 423. Cortex-M0 instructions
Mnemonic Operands Brief description Flags Reference
Table 424. CMSIS intrinsic functions to generate some Cortex-M0 instructions
Instruction CMSIS intrinsic function
CPSIE i void __enable_irq(void)
CPSID i void __disable_irq(void)
ISB void __ISB(void)
DSB void __DSB(void)
DMB void __DMB(void)
NOP void __NOP(void)
REV uint32_t __REV(uint32_t int value)
REV16 uint32_t __REV16(uint32_t int value)
REVSH uint32_t __REVSH(uint32_t int value)
To Next Page
Loading...
Need help?
General
