UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 454 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
LDR Rt, label Load Register from PC-relative
address
- Section 24–24.4.4
LDR Rt, [Rn, <Rm|#imm>] Load Register with word - Section 24–24.4.4
LDRB Rt, [Rn, <Rm|#imm>] Load Register with byte - Section 24–24.4.4
LDRH Rt, [Rn, <Rm|#imm>] Load Register with halfword - Section 24–24.4.4
LDRSB Rt, [Rn, <Rm|#imm>] Load Register with signed byte - Section 24–24.4.4
LDRSH Rt, [Rn, <Rm|#imm>] Load Register with signed
halfword
- Section 24–24.4.4
LSLS {Rd,} Rn, <Rs|#imm> Logical Shift Left N,Z,C Section 24–24.4.5
.3
U {Rd,} Rn, <Rs|#imm> Logical Shift Right N,Z,C Section 24–24.4.5
.3
MOV{S} Rd, Rm Move N,Z Section 24–24.4.5
.5
MRS Rd, spec_reg Move to general register from
special register
- Section 24–24.4.7
.6
MSR spec_reg, Rm Move to special register from
general register
N,Z,C,V Section 24–24.4.7
.7
MULS Rd, Rn, Rm Multiply, 32-bit result N,Z Section 24–24.4.5
.6
MVNS Rd, Rm Bitwise NOT N,Z Section 24–24.4.5
.5
NOP - No Operation - Section 24–24.4.7
.8
ORRS {Rd,} Rn, Rm Logical OR N,Z Section 24–24.4.5
.2
POP reglist Pop registers from stack - Section 24–24.4.4
.6
PUSH reglist Push registers onto stack - Section 24–24.4.4
.6
REV Rd, Rm Byte-Reverse word - Section 24–24.4.5
.7
REV16 Rd, Rm Byte-Reverse packed halfwords - Section 24–24.4.5
.7
REVSH Rd, Rm Byte-Reverse signed halfword - Section 24–24.4.5
.7
RORS {Rd,} Rn, Rs Rotate Right N,Z,C Section 24–24.4.5
.3
RSBS {Rd,} Rn, #0 Reverse Subtract N,Z,C,V Section 24–24.4.5
.1
SBCS {Rd,} Rn, Rm Subtract with Carry N,Z,C,V Section 24–24.4.5
.1
SEV - Send Event - Section 24–24.4.7
.9
STM Rn!, reglist Store Multiple registers,
increment after
- Section 24–24.4.4
.5
Table 423. Cortex-M0 instructions
Mnemonic Operands Brief description Flags Reference
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