Name: NXP Semiconductors LPC11U3x
Brand: NXP Semiconductors
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User manual Rev. 5.5 — 21 December 2016 510 of 523

NXP Semiconductors

UM10462

Chapter 25: Supplementary information

Table 336. Register overview: Watchdog timer (base

address 0x4000 4000) . . . . . . . . . . . . . . . . . .373

Table 337. Watchdog mode register (MOD - 0x4000 4000)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .373

Table 338. Watchdog operating modes selection . . . . . .375

Table 339. Watchdog Timer Constant register (TC - 0x4000

4004) bit description . . . . . . . . . . . . . . . . . . . .375

Table 340. Watchdog Feed register (FEED - 0x4000 4008)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .376

Table 341. Watchdog Timer Value register (TV - 0x4000

400C) bit description. . . . . . . . . . . . . . . . . . . .376

Table 342. Watchdog Clock Select register (CLKSEL -

0x4000 4010) bit description . . . . . . . . . . . . .376

Table 343. Watchdog Timer Warning Interrupt register

(WARNINT - 0x4000 4014) bit description . . .377

Table 344. Watchdog Timer Window register (WINDOW -

0x4000 4018) bit description . . . . . . . . . . . . .377

Table 345. Register overview: SysTick timer (base address

0xE000 E000). . . . . . . . . . . . . . . . . . . . . . . . .380

Table 346. SysTick Timer Control and status register

(SYST_CSR - 0xE000 E010) bit description .381

Table 347. System Timer Reload value register (SYST_RVR

- 0xE000 E014) bit description . . . . . . . . . . . .381

Table 348. System Timer Current value register (SYST_CVR

- 0xE000 E018) bit description . . . . . . . . . . . .381

Table 349. System Timer Calibration value register

(SYST_CALIB - 0xE000 E01C) bit description. . .

382

Table 350. ADC pin description . . . . . . . . . . . . . . . . . . . .383

Table 351. Register overview: ADC (base address 0x4001

C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384

Table 352. A/D Control Register (CR - address

0x4001 C000) bit description . . . . . . . . . . . . .385

Table 353. A/D Global Data Register (GDR - address

0x4001 C004) bit description . . . . . . . . . . . . .386

Table 354. A/D Interrupt Enable Register (INTEN - address

0x4001 C00C) bit description . . . . . . . . . . . . .387

Table 355. A/D Data Registers (DR0 to DR7 - addresses

0x4001 C010 to 0x4001 C02C) bit description. . .

387

Table 356. A/D Status Register (STAT - address

0x4001 C030) bit description . . . . . . . . . . . . .388

Table 357. LPC11U3x/2x/1x flash configurations . . . . . .389

Table 358. ISP entry pins for different boot loader versions .

391

Table 359. CRP levels for USB boot images. . . . . . . . . .395

Table 360. LPC11U1x/2x flash sectors . . . . . . . . . . . . . .397

Table 361. LPC11U3x flash sectors and pages . . . . . . .397

Table 362. Code Read Protection (CRP) options . . . . . .399

Table 363. Code Read Protection hardware/software

interaction . . . . . . . . . . . . . . . . . . . . . . . . . . .399

Table 364. ISP commands allowed for different CRP levels .

400

Table 365. ISP command summary. . . . . . . . . . . . . . . . .401

Table 366. ISP Unlock command . . . . . . . . . . . . . . . . . .401

Table 367. ISP Set Baud Rate command . . . . . . . . . . . .402

Table 368. ISP Echo command . . . . . . . . . . . . . . . . . . . .402

Table 369. ISP Write to RAM command . . . . . . . . . . . . .403

Table 370. ISP Read Memory command . . . . . . . . . . . . 403

Table 371. ISP Prepare sector(s) for write operation

command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

Table 372. ISP Copy command . . . . . . . . . . . . . . . . . . . 405

Table 373. ISP Go command . . . . . . . . . . . . . . . . . . . . . 406

Table 374. ISP Erase sector command . . . . . . . . . . . . . 406

Table 375. ISP Blank check sector command . . . . . . . . 407

Table 376. ISP Read Part Identification command . . . . . 407

Table 377. LPC11U3x/2x/1x device identification numbers .

407

Table 378. ISP Read Boot Code version number command

408

Table 379. ISP Compare command . . . . . . . . . . . . . . . . 408

Table 380. ReadUID command. . . . . . . . . . . . . . . . . . . . 409

Table 381. ISP Return Codes Summary. . . . . . . . . . . . . 409

Table 382. IAP Command Summary . . . . . . . . . . . . . . . 411

Table 383. IAP Prepare sector(s) for write operation

command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Table 384. IAP Copy RAM to flash command. . . . . . . . . 413

Table 385. IAP Erase Sector(s) command . . . . . . . . . . . 413

Table 386. IAP Blank check sector(s) command . . . . . . 414

Table 387. IAP Read Part Identification command . . . . . 414

Table 388. IAP Read Boot Code version number command

414

Table 389. IAP Compare command . . . . . . . . . . . . . . . . 415

Table 390. Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . . . . 415

Table 391. IAP ReadUID command . . . . . . . . . . . . . . . . 415

Table 392. IAP Erase page command . . . . . . . . . . . . . . 416

Table 393. IAP Write EEPROM command . . . . . . . . . . . 416

Table 394. IAP Read EEPROM command . . . . . . . . . . . 416

Table 395. IAP Status codes summary. . . . . . . . . . . . . . 417

Table 396. Memory mapping in debug mode . . . . . . . . . 417

Table 397. Register overview: FMC (base address 0x4003

C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Table 398. EEPROM BIST start address register

(EEMSSTART - address 0x4003 C09C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Table 399. EEPROM BIST stop address register

(EEMSSTOP - address 0x4003 C0A0) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Table 400. EEPROM BIST signature register (EEMSSIG -

address 0x4003 C0A4) bit description. . . . . . 419

Table 401. Flash configuration register (FLASHCFG,

address 0x4003 C010) bit description . . . . . . 420

Table 402. Flash module signature start register

(FMSSTART - 0x4003 C020) bit description . 420

Table 403. Flash module signature stop register (FMSSTOP

- 0x4003 C024) bit description. . . . . . . . . . . . 421

Table 404. FMSW0 register (FMSW0, address: 0x4003

C02C) bit description . . . . . . . . . . . . . . . . . . 421

Table 405. FMSW1 register (FMSW1, address: 0x4003

C030) bit description . . . . . . . . . . . . . . . . . . . 421

Table 406. FMSW2 register (FMSW2, address: 0x4003

C034)

bit

description. . . . . . . . . . . . . . . . . . . 421

Table 407. FMSW3 register (FMSW3, address: 0x4003

40C8) bit description. . . . . . . . . . . . . . . . . . . 421

Table 408. Flash module status register (FMSTAT - 0x4003

CFE0) bit description . . . . . . . . . . . . . . . . . . . 422

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English

NXP Semiconductors LPC11U3x User Manual

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