UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 509 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
0x4000 00[30, 34, 38, 3C]) bit description . . .300
Table 283. CONSET used to configure Master mode . . .305
Table 284. CONSET used to configure Slave mode . . . .306
Table 285. Abbreviations used to describe an I
2
C operation.
308
Table 286. CONSET used to initialize Master Transmitter
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
Table 287. Master Transmitter mode. . . . . . . . . . . . . . . .310
Table 288. Master Receiver mode. . . . . . . . . . . . . . . . . .313
Table 289. ADR usage in Slave Receiver mode . . . . . . .315
Table 290. CONSET used to initialize Slave Receiver mode
315
Table 291. Slave Receiver mode . . . . . . . . . . . . . . . . . .316
Table 292. Slave Transmitter mode. . . . . . . . . . . . . . . . .320
Table 293. Miscellaneous States. . . . . . . . . . . . . . . . . . .322
Table 294. Counter/timer pin description. . . . . . . . . . . . .334
Table 295. Register overview: 16-bit counter/timer 0 CT16B0
(base address 0x4000 C000) . . . . . . . . . . . .335
Table 296. Register overview: 16-bit counter/timer 1 CT16B1
(base address 0x4001 0000) . . . . . . . . . . . .336
Table 297. Interrupt Register (IR, address 0x4000 C000
(CT16B0)) bit description . . . . . . . . . . . . . . . .337
Table 298. Interrupt Register (IR, address 0x4001 0000
(CT16B1)) bit description . . . . . . . . . . . . . . . .337
Table 299. Timer Control Register (TCR, address 0x4000
C004 (CT16B0) and 0x4001 0004 (CT16B1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .337
Table 300: Timer counter registers (TC, address
0x4000 C008 (CT16B0) and 0x4001 0008
(CT16B1)) bit description . . . . . . . . . . . . . . . .338
Table 301: Prescale registers (PR, address 0x4000 C00C
(CT16B0) and 0x4001 000C (CT16B1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .338
Table 302: Prescale counter registers (PC, address
0x4000 C010 (CT16B0) and 0x4001 0010
(CT16B1)) bit description . . . . . . . . . . . . . . . .339
Table 303. Match Control Register (MCR, address 0x4000
C014 (CT16B0) and 0x4001 0014 (CT16B1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .339
Table 304: Match registers (MR[0:3], addresses
0x4000 C018 (MR0) to 0x4000 C024 (MR3)
(CT16B0) and 0x4001 0018 (MR0) to
0x4001 0024 (MR3) (CT16B1)) bit description. . .
340
Table 305. Capture Control Register (CCR, address 0x4000
C028 (CT16B0)) bit description . . . . . . . . . . .341
Table 306. Capture Control Register (CCR, address
0x4001 0028 (CT16B1)) bit description . . . . .341
Table 307: Capture register 0 (CR0, address 0x4000 C02C
(CT16B0) and address 0x4001 002C (CT16B1))
bit description . . . . . . . . . . . . . . . . . . . . . . . . .342
Table 308: Capture register 1 (CR1, address 0x4000 C034
(CT16B0)) bit description . . . . . . . . . . . . . . . .342
Table 309: Capture register 1 (CR1, address 0x4001 0030
(CT16B1)) bit description . . . . . . . . . . . . . . . .343
Table 310. External Match Register (EMR, address 0x4000
C03C (CT16B0) and 0x4001 003C (CT16B1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .343
Table 311. External match control. . . . . . . . . . . . . . . . . . 344
Table 312. Count Control Register (CTCR, address 0x4000
C070 (CT16B0)) bit description . . . . . . . . . . 345
Table 313. Count Control Register (CTCR, address
0x4001 0070 (CT16B1)) bit description . . . . . 346
Table 314. PWM Control Register (PWMC, address 0x4000
C074 (CT16B0) and 0x4001 0074 (CT16B1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 315. Counter/timer pin description . . . . . . . . . . . . 352
Table 316. Register overview: 32-bit counter/timer 0 CT32B0
(base address 0x4001 4000) . . . . . . . . . . . . 353
Table 317. Register overview: 32-bit counter/timer 1 CT32B1
(base address 0x4001 8000) . . . . . . . . . . . . 354
Table 318: Interrupt Register (IR, address 0x4001 4000
(CT32B0)) bit description. . . . . . . . . . . . . . . . 355
Table 319: Interrupt Register (IR, address 0x4001 8000
(CT32B1)) bit description. . . . . . . . . . . . . . . . 355
Table 320: Timer Control Register (TCR, address
0x4001 4004 (CT32B0) and 0x4001 8004
(CT32B1)) bit description. . . . . . . . . . . . . . . . 355
Table 321: Timer counter registers (TC, address
0x4001 4008 (CT32B0) and 0x4001 8008
(CT32B1)) bit description. . . . . . . . . . . . . . . . 356
Table 322: Prescale registers (PR, address 0x4001 400C
(CT32B0) and 0x4001 800C (CT32B1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Table 323: Prescale registers (PC, address 0x4001 4010
(CT32B0) and 0x4001 8010 (CT32B1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Table 324: Match Control Register (MCR, address
0x4001 4014 (CT32B0) and 0x4001 8014
(CT32B1)) bit description. . . . . . . . . . . . . . . . 357
Table 325: Match registers (MR[0:3], addresses
0x4001 4018 (MR0) to 0x4001 4024 (MR3)
(CT32B0) and 0x4001 8018(MR0) to 0x40018024
(MR3) (CT32B1)) bit description . . . . . . . . . . 358
Table 326: Capture Control Register (CCR, address
0x4001 4028 (CT32B0) ) bit description . . . . 358
Table 327: Capture Control Register (CCR, address
0x4001 8028 (CT32B1)) bit description . . . . . 359
Table 328: Capture registers (CR0, addresses
0x4001 402C(CT32B0) and 0x4001 802C
(CT32B1)) bit description. . . . . . . . . . . . . . . . 360
Table 329: Capture register (CR1, address 0x4001 4034
(CT32B0)) bit description. . . . . . . . . . . . . . . . 360
Table 330: Capture register (CR1, address 0x4001 8030
(CT32B1)) bit description. . . . . . . . . . . . . . . . 360
Table 331: External Match Register (EMR, address
0x4001 403C (CT32B0) and 0x4001 803C
(CT32B1)) bit description. . . . . . . . . . . . . . . . 361
Table 332. External match control . . . . . . . . . . . . . . . . . 362
Table 333: Count Control Register (CTCR, address
0x4001 4070 (CT32B0)) bit description . . . . 363
Table 334: Count Control Register (CTCR, address
0x4001 8070 (CT32B1)) bit description . . . . 364
T
a
ble 335: PWM Control Register (PWMC, 0x4001 4074
(CT32B0) and 0x4001 8074 (CT32B1)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
To Next Page
Loading...
Need help?
General
