UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 353 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 316. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 4000)
Name Access Address
offset
Description Reset
value
[1]
Reference
IR R/W 0x000 Interrupt Register. The IR can be written to clear interrupts. The IR
can be read to identify which of eight possible interrupt sources are
pending.
0 Table 318
TCR R/W 0x004 Timer Control Register. The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset
through the TCR.
0 Table 320
TC R/W 0x008 Timer Counter. The 32-bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.
0 Table 321
PR R/W 0x00C Prescale Register. When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
0 Table 322
PC R/W 0x010 Prescale Counter. The 32-bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
0 Table 323
MCR R/W 0x014 Match Control Register. The MCR is used to control if an interrupt is
generated and if the TC is reset when a Match occurs.
0 Table 324
MR0 R/W 0x018 Match Register 0. MR0 can be enabled through the MCR to reset the
TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC.
0 Table 325
MR1 R/W 0x01C Match Register 1. See MR0 description. 0 Table 325
MR2 R/W 0x020 Match Register 2. See MR0 description. 0 Ta ble 325
MR3 R/W 0x024 Match Register 3. See MR0 description. 0 Ta ble 325
CCR R/W 0x028 Capture Control Register. The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether
or not an interrupt is generated when a capture takes place.
0 Table 326
CR0 RO 0x02C Capture Register 0. CR0 is loaded with the value of TC when there is
an event on the CT32B0_CAP0 input.
0 Table 328
- 0x030 Reserved - -
CR1 - 0x034 Capture Register 1. CR1 is loaded with the value of TC when there is
an event on the CT32B0_CAP1 input.
- Table 329
- - 0x038 Reserved. - -
EMR R/W 0x03C External Match Register. The EMR controls the match function and
the external match pins CT32Bn_MAT[3:0].
0 Table 331
- - 0x040 -
0x06C
Reserved. - -
CTCR R/W 0x070 Count Control Register. The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s)
for counting.
0 Table 333
PWMC R/W 0x074 PWM Control Register. The PWMCON enables PWM mode for the
external match pins CT32Bn_MAT[3:0].
0 Table 335
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