UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 508 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
Table 230. USART Receiver Buffer Register when
DLAB = 0, Read Only (RBR - address
0x4000 8000) bit description . . . . . . . . . . . . .244
Table 231. USART Transmitter Holding Register when
DLAB = 0, Write Only (THR - address
0x4000 8000) bit description . . . . . . . . . . . . .244
Table 232. USART Divisor Latch LSB Register when
DLAB = 1 (DLL - address 0x4000 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Table 233. USART Divisor Latch MSB Register when
DLAB = 1 (DLM - address 0x4000 8004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Table 234. USART Interrupt Enable Register when
DLAB = 0 (IER - address 0x4000 8004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .245
Table 235. USART Interrupt Identification Register Read
only (IIR - address 0x4004 8008) bit description
246
Table 236. USART Interrupt Handling . . . . . . . . . . . . . . .247
Table 237. USART FIFO Control Register Write only (FCR -
address 0x4000 8008) bit description. . . . . . .249
Table 238. USART Line Control Register (LCR - address
0x4000 800C) bit description . . . . . . . . . . . .249
Table 239. USART Modem Control Register (MCR - address
0x4000 8010) bit description . . . . . . . . . . . . .250
Table 240. Modem status interrupt generation . . . . . . . .252
Table 241. USART Line Status Register Read only (LSR -
address 0x4000 8014) bit description . . . . . .253
Table 242: USART Modem Status Register (MSR - address
0x4000 8018) bit description . . . . . . . . . . . . .255
Table 243. USART Scratch Pad Register (SCR - address
0x4000 801C) bit description . . . . . . . . . . . . .255
Table 244. Auto-baud Control Register (ACR - address
0x4000 8020) bit description . . . . . . . . . . . . .256
Table 245: IrDA Control Register (ICR - 0x4000 8024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .259
Table 246: IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . .259
Table 247. USART Fractional Divider Register (FDR -
address 0x4000 8028) bit description. . . . . . .260
Table 248. Fractional Divider setting look-up table . . . . .263
Table 249. USART Oversampling Register (OSR - address
0x4000 802C) bit description . . . . . . . . . . . . .264
Table 250. USART Transmit Enable Register (TER - address
0x4000 8030) bit description . . . . . . . . . . . . .265
Table 251. USART Half duplex enable register (HDEN -
addresses 0x4000 8040) bit description . . . .265
Table 252. Smart Card Interface Control register (SCICTRL -
address 0x4000 8048) bit description . . . . . .266
Table 253. USART RS485 Control register (RS485CTRL -
address 0x4000 804C) bit description . . . . .266
Table 254. USART RS-485 Address Match register
(RS485ADRMATCH - address 0x4000 8050) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .267
Table 255. USART RS-485 Delay value register (RS485DLY
- address 0x4000 8054) bit description . . . . .268
Table 256. USART Synchronous mode control register
(SYNCCTRL - address 0x4000 8058) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .268
Table 257. SSP/SPI pin descriptions . . . . . . . . . . . . . . . 276
Table 258. Register overview: SSP/SPI0 (base address
0x4004 0000). . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 259. Register overview: SSP/SPI1 (base address
0x4005 8000). . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 260. SSP/SPI Control Register 0 (CR0 - address
0x4004 0000 (SSP0) and 0x4005 8000 (SSP1))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 261. SSP/SPI Control Register 1 (CR1 - address
0x4004 0004 (SSP0) and 0x4005 8004 (SSP1))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 262. SSP/SPI Data Register (DR - address
0x4004 0008 (SSP0) and 0x4005 8008 (SSP1))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 263. SSP/SPI Status Register (SR - address
0x4004 000C (SSP0) and 0x4005 800C (SSP1))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 264. SSP/SPI Clock Prescale Register (CPSR -
address 0x4004 0010 (SSP0) and 0x4005 8010
(SSP1)) bit description. . . . . . . . . . . . . . . . . . 280
Table 265. SSP/SPI Interrupt Mask Set/Clear register (IMSC
- address 0x4004 0014 (SSP0) and 0x4005 8014
(SSP1)) bit description. . . . . . . . . . . . . . . . . . 281
Table 266. SSP/SPI Raw Interrupt Status register (RIS -
address 0x4004 0018 (SSP0) and 0x4005 8018
(SSP1)) bit description. . . . . . . . . . . . . . . . . . 281
Table 267. SSP/SPI Masked Interrupt Status register (MIS -
address 0x4004 001C (SSP0) and 0x4005 801C
(SSP1)) bit description. . . . . . . . . . . . . . . . . . 282
Table 268. SSP/SPI interrupt Clear Register (ICR - address
0x4004 0020 (SSP0) and 0x4005 8020 (SSP1))
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 269. I
2
C-bus pin description . . . . . . . . . . . . . . . . . 292
Table 270. Register overview: I
2
C (base address 0x4000
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 271. I
2
C Control Set register (CONSET - address
0x4000 0000) bit description . . . . . . . . . . . . . 293
Table 272. I
2
C Status register (STAT - 0x4000 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 273. I
2
C Data register (DAT - 0x4000 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 274. I
2
C Slave Address register 0 (ADR0-
0x4000 000C) bit description . . . . . . . . . . . . . 296
Table 275. I
2
C SCL HIGH Duty Cycle register (SCLH -
address 0x4000 0010) bit description . . . . . . 296
Table 276. I
2
C SCL Low duty cycle register (SCLL -
0x4000 0014) bit description . . . . . . . . . . . . . 296
Table 277. SCLL + SCLH values for selected I
2
C clock
values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 278. I
2
C Control Clear register (CONCLR -
0x4000 0018) bit description . . . . . . . . . . . . . 297
Table 279. I
2
C Monitor mode control register (MMCTRL -
0x4000 001C) bit description . . . . . . . . . . . . . 298
Table 280. I
2
C Slave Address registers (ADR[1, 2, 3]-
0x4000 00[20, 24, 28]) bit description . . . . . . 299
Table 281. I
2
C Data buffer register (DATA_BUFFER -
0x4000 002C) bit description . . . . . . . . . . . . . 300
Table 282. I
2
C Mask registers (MASK[0, 1, 2, 3] -
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