Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 103
UG366 (v2.5) January 17, 2011
Reference Clock Selection
document describes the reference clocking architecture of the Virtex-6 FPGA GTX
transceivers.
Reference clock features include:
• Clock routing for north and south bound clocks.
• Clock inputs available per GTX PLL.
• Static or dynamic selection of the reference clock for the transmitter and receiver
PLLs.
Figure 2-2 shows the Quad architecture with four GTX transceivers, two dedicated
reference clock pin pairs, and dedicated north/south reference clock routing. Each GTX
transceiver in a Quad has seven clock inputs available:
• Two local reference clock pin pairs, MGTREFCLK[0/1]
• Two reference clock pin pairs from the Quads above, SOUTHREFCLK[0/1]
• Two reference clocks pin pairs or below, NORTHREFCLK[0/1]
• Internal to each GTX transceiver, the clock from the receiver can be forwarded to the
transmit PLL reference clock, CAS_CLK. CAS_CLK must only be used for diagnostics
purposes.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English