Xilinx Virtex-6 FPGA

104 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 2: Shared Transceiver Features
X-Ref Target - Figure 2-2
Figure 2-2: Conceptual View of GTX Transceiver Reference Clocking
UG366_c2_01_051509
GTX2
GTX1
MGTREFCLK0
Q
(n+1)
NorthClk1
Q
(n+1)
NorthClk0
Q
(n+1)
SouthClk1
Q
(n+1)
SouthClk0
Q
(n+1)
RefClk1
Q
(n+1)
RefClk0
Controlled
by Software
MGTREFCLK0[P/N]
1
MGTREFCLK1 GREFCLK PERFCLK SOUTHREFCLK0 SOUTHREFCLK1 NORTHREFCLK0 NORTHREFCLK1
GTX0
CAS_CLK
NA
TX PLL
RX PLL
TX PLL
RX PLL
TX PLL
RX PLL
TX PLL
RX PLL
GTX3
Q
(n)
Q
(n+1)
CAS_CLK
NA
MGTREFCLK1[P/N]
MGTREFCLK0[P/N]
MGTREFCLK1[P/N]
PERFCLK
GREFCLK
MGTREFCLK0[P/N]
GTX0
CAS_CLK
NA
MGTREFCLK1[P/N]
PERFCLK
GREFCLK
0
01
Q
(n)
NorthClk1
Q
(n)
NorthClk0
Q
(n)
SouthClk1
Q
(n)
SouthClk0
Q
(n)
RefClk1
Q
(n)
RefClk0
Controlled
by Software
1
GTX3
Q
(n-1)
CAS_CLK
NA
PERFCLK
GREFCLK
0
01
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