Xilinx Virtex-6 FPGA

116 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 2: Shared Transceiver Features
TX_TDCC_CFG 2-bit
Binary
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
TXPLL_COM_CFG
RXPLL_COM_CFG
24-bit
Hex
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
TXPLL_CP_CFG
RXPLL_CP_CFG
8-bit
Hex
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
TXPLL_DIVSEL_FB
RXPLL_DIVSEL_FB
Integer This attribute is N2 in Figure 2-9. This attribute specifies one of the two PLL
feedback dividers. Common settings are 1, 2, 4, and 5.
TXPLL_DIVSEL_OUT
RXPLL_DIVSEL_OUT
Integer This attribute is D in Equation 2-2. It specifies the value of the PLL output divider,
which resides in the clock divider block. Valid settings are 1, 2, and 4.
TXPLL_DIVSEL_REF
RXPLL_DIVSEL_REF
Integer This attribute is M in Figure 2-9. It specifies the value for the reference clock input
divider. Common settings are 1 and 2.
TXPLL_DIVSEL45_FB
RXPLL_DIVSEL45_FB
Integer This attribute is N1 in Figure 2-9. It specifies one of the two PLL feedback dividers.
Valid settings are 4 and 5.
TXPLL_LKDET_CFG
RXPLL_LKDET_CFG
3-bit
Binary
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
TXPLL_SATA 2-bit
Binary
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
Table 2-9: PLL Attributes (Cont’d)
Attribute Type Description
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