Xilinx Virtex-6 FPGA User Manual

156 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 3: Transmitter
TXENPMAPHASEALIGN In Async When activated, the GTX transmitter can align its XCLK
with its TXUSRCLK. This also allows the XCLKs in
multiple GTX transmitters to be synchronized to reduce
TX skew between them.
TXOUTCLK Out N/A This output is the recommended clock to the FPGA logic.
The TXOUTCLK_CTRL attribute is the input selector for
TXOUTCLK. When TXOUTCLK is used as the clock
source for TXUSRCLK in TX buffer bypass mode,
TXOUTCLK_CTRL must select either
TXPLLREFCLK_DIV1 or TXPLLREFCLK_DIV2 for TX
phase alignment to be effective.
TXPLLLKDET Out Async Indicates that the VCO rate is within acceptable tolerances
of the desired rate when High. The GTX transceiver does
not operate reliably until this condition is met.
TXPLLLKDETEN In Async Enables the TX PLL lock detector. It must be tied High.
TXPMASETPHASE In Async When activated, TXPMASETPHASE aligns XCLK with
TXUSRCLK allowing the TX buffer to be bypassed. While
TXPMASETPHASE is High, the phase of XCLK generally
changes to affect its alignment with TXUSRCLK. This in
turn implies a change in phase on the TX serial lines,
which appears as temporary, occasional changes in the
nominal UI. Thus, the UI might be observed to vary by
several ps when TXPMASETPHASE is High.
TXUSRCLK In N/A Use this port to provide a clock for the internal TX PCS
datapath. The rate for TXUSRCLK depends on
TX_DATA_WIDTH.
Table 3-18: TX Buffer Bypass Ports (Cont’d)
Port Dir Clock Domain Description
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English