Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 187
UG366 (v2.5) January 17, 2011
RX Analog Front End
Table 4-5 outlines the recommended settings for RX termination in Use Mode 2. Figure 4-4
shows the Use Mode 2 configuration.
X-Ref Target - Figure 4-3
Figure 4-3: RX Termination Use Mode 1 Configuration
UG366_c4_03_071009
~100 nF
nominal
50Ω
nominal
50Ω
FPGABoard
MGTAVTT_*
MGTAVTT_*
GND
~100 nF
nominal 7 pF
nominal 7 pF
ESD Diodes
ESD Diodes
nominal
50 KΩ
nominal
50 KΩ
V
CM
2/3 MGTAVTT_*
Table 4-5: RX Termination Use Mode 2 Configuration and Notes
Use Mode
External
AC
Coupling
Term
Voltage
Internal AC
Coupling
Internal
Bias
Max
Swing
mV
DPP
Suggested Protocols and Usage Notes
2 On VTT Off 800 mV 1200 Protocol: Backplane, CEI-6 (1200 mV
DPP
),
Wireless, Serial RapidIO, DisplayPort
(0.4V/0.6V/0.8V option).
Protocols such as HD-SDI and SD-SDI can also
use this termination mode if cable equalizer
devices are used between SDI cable and the
Xilinx FPGA SerDes interface. In this
configuration, the signal swing from the cable
equalizer device is usually less than 1200 mV.
Attribute Settings:
AC_CAP_DIS = TRUE
RCV_TERM_GND = FALSE
RCV_TERM_VTTRX = TRUE
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English