Xilinx Virtex-6 FPGA User Manual

22 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
X-Ref Target - Figure 1-3
Figure 1-3: Quad Configuration
From/To Adjacent Quad
From/To Adjacent Quad
UG366_c1_03_051509
TX-P2S
RX0
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX0
TX-P2S
RX1
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX1
TX-P2S
RX2
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX2
TX-P2S
RX3
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX3
MGTREFCLK0
MGTREFCLK1
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English