Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 21
UG366 (v2.5) January 17, 2011
Overview
•The Virtex-6 FPGA Configuration User Guide provides more information on the
Configuration and Clock, MMCM, and I/O blocks.
•The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide provides detailed
information on the Ethernet MAC.
Figure 1-2 illustrates the location of the GTX transceiver inside the Virtex-6 XC6VLX75T
FPGA.
GTX transceivers are clustered together in a set of four called a Quad or Q. Figure 1-3
illustrates the clustering of four GTX transceivers to a Quad. Refer to Implementation,
page 41 for placement information and the mapping of each transceiver into a specific
Quad.
X-Ref Target - Figure 1-2
Figure 1-2: GTX Transceiver Inside the Virtex-6 XC6VLX75T FPGA
MMCM
MMCM
MMCM
I/O
Column
I/O
Column
I/O
Column
Configuration
Virtex-6 FPGA (XC6VLX75T)
UG366_c1_02_051509
GTXE1
Column
GTXE1_
X0Y11
GTXE1_
X0Y10
GTXE1_
X0Y9
GTXE1_
X0Y8
GTXE1_
X0Y7
GTXE1_
X0Y6
GTXE1_
X0Y5
GTXE1_
X0Y4
GTXE1_
X0Y3
GTXE1_
X0Y2
GTXE1_
X0Y1
GTXE1_
X0Y0
Ethernet
MAC
Ethernet
MAC
Ethernet
MAC
Ethernet
MAC
Integrated
Block for
PCI Express
Operation
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English