Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 29
UG366 (v2.5) January 17, 2011
Port and Attribute Summary
TX Receiver Detect Support for PCI Express Designs
Ports:
• PHYSTATUS
• RXPOWERDOWN[1:0]
• TXPOWERDOWN[1:0]
• RXSTATUS[2:0]
• TXDETECTRX
page 179
page 180
page 180
page 180
page 180
TX OOB
Ports:
• COMFINISH
• TXCOMINIT
• TXCOMSAS
• TXCOMWAKE
• TXELECIDLE
• TXPOWERDOWN[1:0]
page 181
page 181
page 181
page 181
page 181
page 181
Attributes:
• COM_BURST_VAL
• TXPLL_SATA
page 181
page 181
RX AFE
Ports:
• RXN
• RXP
page 185
page 185
Attributes:
• AC_CAP_DIS
• CM_TRIM[1:0]
• RCV_TERM_GND
• RCV_TERM_VTTRX
• TERMINATION_CTRL[4:0]
• TERMINATION_OVRD
page 185
page 185
page 185
page 185
page 186
page 186
RX OOB
Ports:
• COMINITDET
• COMSASDET
• COMWAKEDET
• GATERXELECIDLE
• IGNORESIGDET
• RXELECIDLE
• RXSTATUS[2:0]
• RXVALID
page 192
page 192
page 192
page 192
page 192
page 192
page 193
page 193
Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English