Xilinx Virtex-6 FPGA

28 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
Ports:
• GTXTEST[1]
• MGTREFCLKFAB[0]
• O
• ODIV2
• PHYSTATUS
• TXOUTCLK
• TXOUTCLKPCS
• TXRATE
• TXRATEDONE
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Attributes:
• TRANS_TIME_RATE
• TX_EN_RATE_RESET_BUF
• TXOUTCLK_CTRL
• TXPLL_DIVSEL_OUT
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TX Configurable Driver
Ports:
• TXBUFDIFFCTRL[2:0]
• TXDEEMPH
• TXDIFFCTRL[3:0]
• TXELECIDLE
• TXINHIBIT
• TXMARGIN[2:0]
• TXPDOWNASYNCH
• TXPOSTEMPHASIS[4:0]
• TXPREEMPHASIS[3:0]
• TXP TXN
• TXSWING
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Attributes:
• TX_DEEMPH_0[4:0]
• TX_DEEMPH_1[4:0]
• TX_DRIVE_MODE
• TX_MARGIN_FULL_0[6:0]
• TX_MARGIN_FULL_1[6:0]
• TX_MARGIN_FULL_2[6:0]
• TX_MARGIN_FULL_3[6:0]
• TX_MARGIN_FULL_4[6:0]
• TX_MARGIN_LOW_0[6:0]
• TX_MARGIN_LOW_1[6:0]
• TX_MARGIN_LOW_2[6:0]
• TX_MARGIN_LOW_3[6:0]
• TX_MARGIN_LOW_4[6:0]
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
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