Xilinx Virtex-6 FPGA

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 175
UG366 (v2.5) January 17, 2011
TX Configurable Driver
TXPDOWNASYNCH In Async Determines if TXELECIDLE and TXPOWERDOWN should be
treated as synchronous or asynchronous signals. Enables
compliance during cold and warm PCI Express resets.
0: Sets TXELECIDLE and TXPOWERDOWN to synchronous
mode.
1: Sets TXELECIDLE and TXPOWERDOWN to asynchronous
mode.
TXPOSTEMPHASIS[4:0] In Async Transmitter Post-Cursor TX Pre-Emphasis Control. The default is
user specified. All listed values (dB) are typical.
Table 3-31: TX Configurable Driver Ports (Cont’d)
Port Dir Clock Domain Description
[4:0] dB (Post-Emphasis Magnitude)
00000 0.18
00001 0.19
00010 0.18
00011 0.18
00100 0.18
00101 0.18
00110 0.18
00111 0.18
01000 0.19
01001 0.2
01010 0.39
01011 0.63
01100 0.82
01101 1.07
01110 1.32
01111 1.6
10000 1.65
10001 1.94
10010 2.21
10011 2.52
10100 2.76
10101 3.08
10110 3.41
10111 3.77
11000 3.97
11001 4.36
11010 4.73
11011 5.16
11100 5.47
11101 5.93
11110 6.38
11111 6.89
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